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PDF IDT49C466 Data sheet ( Hoja de datos )

Número de pieza IDT49C466
Descripción 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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Integrated Device Technology, Inc.
64-BIT FLOW-THRU
ERROR DETECTION
AND CORRECTION UNIT
IDT49C466
IDT49C466A
FEATURES:
• 64-bit wide Flow-thruEDC
• Separate System and Memory Data Input/Output Buses
• — Error Detect Time: 10ns
— Error Correct Time: 15ns
• Corrects all single bit errors; Detects all double bit errors
and some multiple bit errors
• Configurable 16-deep bus read/write FIFOs with flags
• Simultaneous check bit generation and correction of memory
data
• Supports partial word writes on byte boundaries
• Low noise output
• Sophisticated error diagnostics and error logging
• Parity generation on system data bus
• 208-pin Plastic Quad Flatpack
DESCRIPTION:
The IDT49C466/A 64-bit Flow-thruEDC is a high-speed
error detection and correction unit that ensures data integrity
in memory systems. The flow-thru architecture, with separate
system and memory data buses, is ideally suited for pipelined
memory systems.
Implementing a modified Hamming code, the
IDT49C466/A corrects all single bit hard and soft errors, and
detects all double bit errors. The read/write FIFOs can store
up to sixteen words. FIFO full and empty flags indicate
whether additional data can be written to or read from the
EDC.
Check bit generation for partial word writes on byte bound-
aries is supported on the IDT49C466/A.
Diagnostic features include a check bit register, syndrome
registers, a four bit error counter which logs up to 15 errors,
and an error data register which stores the complete error data
word. Parity can be generated and checked on the system
bus by the IDT49C466/A.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
ERR
MERR
READ BUFFER
16 WORDS BY
M 64 M
UU
X MD X
LATCH
OUT
CHECK-BIT
COMPARATOR &
SYNDROME
GENERATOR &
ERROR
DETECTOR
ERROR
CORRECT
DIAGNOSTIC
& STATUS
REGISTERS
MD
CHECK-BIT
GENERATOR
MD
CHK-BIT
LATCH
MD
LATCH
IN
CBI0-7
SD0-63
PARITY
P0-7
WRITE BACK PATH
SD
LATCH
IN
WRITE
BUFFER
16 WORDS BY
72
PARITY
GENERATE &
PARITY CHECK
M
U
X
B
Y
T
E
M
U
X
The IDT logo is a registered trademark and Flow-thruEDC is a trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
11.7
SD
CHECK-BIT
GENERATOR
SD
LATCH
OUT
SD
CHK-BIT
LATCH
MD0-63
CBSYN0-7
2617 drw 01
AUGUST 1996
DSC-2617/9
1

1 page




IDT49C466 pdf
IDT49C466/A Flow-thruEDC
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION (Continued)
Pin Name
RBSEL
RBEN
RBREN
CBSEL
MEN
Clock Inputs
MCLK
SCLK
SYNCLK
I/O
I
I
I
I
I
I
I
I
Status Outputs
WBEF
WBFF
RBEF
RBHF
O
O
O
O
RBFF
ERR
MERR
PERR
Power Supply
VCC
GND
O
O
O
O
P
P
Description
Read FIFO Select: when HIGH, read FIFO is selected (data goes through read FIFO, not MD output
latch). When LOW, the MD output latch is selected.
Read FIFO Enable: when LOW, allows data to be written into the read FIFO on the LOW-to-HIGH
transition of the memory clock.
Read FIFO Enable: when LOW, allows data to be read from the read FIFO on the LOW-to-HIGH
transition of SCLK
Checkbit Syndrome Output Enable: Controls the CBSYN output buffer.When HIGH, the buffer is
enabled. When CBSEL is LOW, MOE controls the buffer.
Mode Enable Input: when LOW, SD0-15 is loaded into the EDC mode register on the LOW-to-HIGH
transition of the SCLK. This pin must be held LOW for the entire SCLK HIGH period, as shown in Figure
4.
Memory Clock: on the LOW-to-HIGH transition of MCLK, memory data is written to the read FIFO
when RBEN is LOW. Data is read from the write FIFO when WBREN is LOW, on the LOW-to-HIGH
transition of MCLK.
System Clock: on the LOW-to-HIGH transition of the SCLK, data is read from the read FIFO when
RBREN is LOW. Data on the system data bus is written into the write FIFO when WBEN is LOW on
the LOW-to-HIGH transition of SCLK. Clocks data into mode register when MEN is LOW.
Syndrome Clock: Used to load diagnostic registers. When an error occurs, Error Counter is
incremented on the rising SYNCLK edge (up to 15 errors). On the first error after a diagnostic reset,
SYNCLK rising edge clocks data into Check Bit, Syndrome, Error Type and Error Data registers. One
of the syndrome registers has new data clocked in on every SYNCLK rising edge.
Write FIFO Empty Flag: when LOW, indicates that the write FIFO is empty. After a reset, the WBEF
goes LOW.
Write FIFO Full Flag: when LOW, indicates that the write FIFO is full. After a reset, WBFF goes HIGH.
Read FIFO Empty Flag: when LOW, indicates that the read FIFO is empty. After a reset, the RBEF
goes LOW.
Read FIFO Half-full Flag: when LOW, indicates that there are eight or more data words (in the 16-
deep configuration) or four or more data words (in the dual 8-deep configuration) in the read FIFO. The
flag will return HIGH when less than eight (or four) data words are in the FIFO.
Read FIFO Full Flag: when LOW, indicates that the read FIFO is full. After a reset, RBFF goes HIGH.
Error Flag: when ERR is LOW, a data error is indicated. The ERR is not latched internally.
Multiple Error Flag: when MERR is LOW, a multiple data error is indicated. The MERR is not latched
internally.
Parity Error Flag: when LOW, indicates a parity error on the system data bus input.
Power Supply Voltage.
Ground.
2617 tbl 02
11.7 5

5 Page





IDT49C466 arduino
IDT49C466/A Flow-thruEDC
ERROR DETECTION AND CORRECTION UNIT
MODE BIT 0
CLEAR
COMMERCIAL TEMPERATURE RANGES
Diag. Regs.
Error Data Regs.
SYNCLK
64
WFIFO
BE0-7
BE0-7
WBSEL
Fig 3. Memory Initialization using Diagnostic Output/Error Data Output Mode
DIAGNOSTIC OUTPUT DATA FORMAT
TO SD BUS
37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
Syndrome
(on every error)
Error
Type
(on
Error
Count
Syndrome
(on 1st error)
Checkbit
(on 1st error only)
1st
error
only)
7 6 54 32 10
Checkbit
(from checkbit latch)
* Bit #28 = 1 If "Error" condition
Bit #29 = 1 If "Multiple bit Error" condition FROM DIAGNOSTIC REGISTERS
Diagnostics
The diagnostic ability of the IDT49C466 rests on a set of 6
registers that provide error logging information. These include
the checkbit register, error count register, error type register,
2 syndrome registers and the error data register. Data is
clocked into each of these registers by SYNCLK. The error
data register, checkbit register, error type register and one of
the syndrome registers are reloaded only in the case of the
first error after a clear. The other syndrome register and the
error count register are reloaded on every error condition
SYNCLK edge. The contents of the Error Data register can be
read only in Error Data Output mode. The contents of the other
diagnostic registers as well as the checkbit latch can be read
in Diagnostic Output mode.
Parity
The IDT49C466 provides a parity check and generation
facility. On a memory read the EDC generates parity bits for
each data byte and outputs the parity byte on the parity bus,
P0-7. During a memory write, parity is checked by comparing
the parity bits input on P0-7 and the parity bits generated from
the input data word. A discrepancy between these two causes
the PERR flag to be asserted. In the case of partial word writes,
the PERR flag is based on the parity bits Px and data bytes
input on SD bus.
DIAG.
REGISTER
CHECKBIT
SYNDROME
(On 1st ERR)
ERR CNT
ERR TYPE
SYNDROME
(On every
ERROR)
LOADED
BY
SYNCLK
SYNCLK
SYNCLK
SYNCLK
SYNCLK
2617 drw 07
CONDITION
OUTPUT
ONLY ON 1st
ERROR
ONLY ON 1st
ERROR
SD8-15
SD16-23
ON EVERY
ERROR (Up to
15 ERRORS)
SD24-27
ONLY ON 1st
ERROR
SD28-29
ON EVERY
ERROR
SD30-37
11.7 11

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