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PDF IDT29FCT521CT Data sheet ( Hoja de datos )

Número de pieza IDT29FCT521CT
Descripción MULTILEVEL PIPELINE REGISTERS
Fabricantes Integrated Device 
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MULTILEVEL
PIPELINE REGISTERS
IDT29FCT520AT/BT/CT/DT
IDT29FCT521AT/BT/CT/DT
Integrated Device Technology, Inc.
FEATURES:
• A, B, C and D speed grades
• Low input and output leakage 1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, SSOP, QSOP, CERPACK and
LCC packages
DESCRIPTION:
The IDT29FCT520AT/BT/CT/DT and IDT29FCT521AT/
BT/CT/DT each contain four 8-bit positive edge-triggered
registers. These may be operated as a dual 2-level or as a
single 4-level pipeline. A single 8-bit input is provided and any
of the four registers is available at the 8-bit, 3-state output.
These devices differ only in the way data is loaded into and
between the registers in 2-level operation. The difference is
illustrated in Figure 1. In the IDT29FCT520AT/BT/CT/DT
when data is entered into the first level (I = 2 or I = 1), the
existing data in the first level is moved to the second level. In
the IDT29FCT521AT/BT/CT/DT, these instructions simply
cause the data in the first level to be overwritten. Transfer of
data to the second level is achieved using the 4-level shift
instruction (I = 0). This transfer also causes the first level to
change. In either part I=3 is for hold.
FUNCTIONAL BLOCK DIAGRAM
D0 -D7
8
I0,I1 2
REGISTER
CONTROL
CLK 1
OCTAL REG. A1
OCTAL REG. A2
MUX
OCTAL REG. B1
OCTAL REG. B2
S0 ,S1 2
MUX
OE
8
Y0 -Y7
2619 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994 Integrated Device Technology, Inc.
6.2
APRIL 1994
DSC-4215/4
1

1 page




IDT29FCT521CT pdf
IDT29FCT520AT/BT/CT/DT, 521AT/BT/CT/DT
MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
tPHL
tPLH
tPHL
tPLH
tSU
tH
tSU
tH
tPHZ
tPLZ
tPZH
tPZL
tW
Parameter
Propagation Delay
CLK to Yn
Propagation Delay
S0 or S1 to Yn
Set-up Time, HIGH or LOW
Dn to CLK
Hold Time, HIGH or LOW
Dn to CLK
Set-up Time, HIGH or LOW
I0 or I1 to CLK
Hold Time, HIGH or LOW
I0 or I1 to CLK
Output Disable Time
Output Enable Time
Clock Pulse Width
HIGH or LOW
Condition(1)
CL = 50pF
RL = 500
FCT520AT/521AT
Com'l.
Mil.
Min.(2) Max. Min.(2) Max.
FCT520BT/521BT
Com'l.
Mil.
Min.(2) Max. Min.(2) Max.
Unit
2.0 14.0 2.0 16.0 2.0 7.5 2.0 8.0 ns
2.0 13.0 2.0 15.0 2.0 7.5 2.0 8.0 ns
5.0 — 6.0 — 2.5 — 2.8 — ns
2.0 — 2.0 — 2.0 — 2.0 — ns
5.0 — 6.0 — 4.0 — 4.5 — ns
2.0 — 2.0 — 2.0 — 2.0 — ns
1.5 12.0 1.5 13.0 1.5 7.0 1.5 7.5 ns
1.5 15.0 1.5 16.0 1.5 7.5 1.5 8.0 ns
7.0 — 8.0 — 5.5 — 6.0 — ns
2619 tbl 07
FCT520CT/521CT
Com'l.
Symbol
Parameter
Condition(1) Min.(2) Max.
tPHL Propagation Delay
tPLH CLK to Yn
CL = 50pF
RL = 500
2.0 6.0
tPHL Propagation Delay
tPLH S0 or S1 to Yn
2.0 6.0
tSU Set-up Time, HIGH or LOW
Dn to CLK
2.5 —
tH Hold Time, HIGH or LOW
Dn to CLK
2.0 —
tSU Set-up Time, HIGH or LOW
I0 or I1 to CLK
4.0 —
tH Hold Time, HIGH or LOW
I0 or I1 to CLK
2.0 —
tPHZ Output Disable Time
tPLZ
1.5 6.0
tPZH Output Enable Time
tPZL
1.5 6.0
tW Clock Pulse Width
HIGH or LOW(3)
5.5 —
NOTES:
1. See test circuit and waveforms.
2. Minimum units are guaranteed but not tested on Propagation Delays.
Mil.
Min.(2) Max.
2.0 7.0
2.0 7.0
2.8 —
2.0 —
4.5 —
2.0 —
1.5 6.0
1.5 7.0
6.0 —
FCT520DT/521DT
Com'l.
Mil.
Min.(2) Max. Min.(2) Max.
Unit
2.0 5.2 — — ns
2.0 4.8 — — ns
1.5 — — — ns
1.0 — — — ns
2.0 — — — ns
1.0 — — — ns
1.5 4.8 — — ns
1.5 4.0 — — ns
3.0 — — — ns
2619 tbl 08
6.2 5

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