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PDF IDT2309A-1HPGI Data sheet ( Hoja de datos )
| Número de pieza | IDT2309A-1HPGI | |
| Descripción | 3.3V ZERO DELAY CLOCK BUFFER | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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IDT2309A
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY
CLOCK BUFFER
IDT2309A
FEATURES:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five and one bank of
four outputs
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2309A-1 for Standard Drive
• IDT2309A-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2309A is a 16-pin version of the IDT2305A. The IDT2309A
accepts one reference input, and drives two banks of four low skew clocks.
The -1H version of this device operates up to 133MHz frequency and has
higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT2309A enters power down. In this mode, the device will draw less than
12µA for Commercial Temperature range and less than 25µA for Industrial
temperature range, and the outputs are tri-stated.
The IDT2309A is characterized for both Industrial and Commercial
operation.
1
REF
PLL
16 CLKOUT
2 CLKA1
3 CLKA2
14 CLKA3
15
CLKA4
S2 8
S1 9
Control
Logic
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2004 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
6 CLKB1
7 CLKB2
10 CLKB3
11 CLKB4
JULY 2004
DSC - 6588/4
1 page  
IDT2309A
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS (2309A-1) - INDUSTRIAL(1,2)
Symbol
Parameter
Conditions
Min.
t1 Output Frequency
10pF Load
10
30pF Load
10
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
t3 Rise Time
Measured between 0.8V and 2V
—
t4 Fall Time
Measured between 0.8V and 2V
—
t5 Output to Output Skew
All outputs equally loaded
—
t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2
—
t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT2309A only) 1
t7 Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
tJ Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
—
tLOCK PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
Typ. Max.
— 133
— 100
50 60
— 2.5
— 2.5
— 250
0 ±350
5 8.7
0 700
— 200
—1
Unit
MHz
%
ns
ns
ps
ps
ns
ps
ps
ms
SWITCHING CHARACTERISTICS (2309A-1H) - INDUSTRIAL(1,2)
Symbol
Parameter
Conditions
Min.
t1 Output Frequency
10pF Load
30pF Load
10
10
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT <50MHz
45
t3 Rise Time
Measured between 0.8V and 2V
—
t4 Fall Time
Measured between 0.8V and 2V
—
t5 Output to Output Skew
All outputs equally loaded
—
t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2
—
t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT2309A only) 1
t7 Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
t8 Output Slew Rate
Measured between 0.8V and 2V using Test Circuit 2
1
tJ Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
—
tLOCK PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
Typ. Max.
— 133
— 100
50 60
50 55
— 1.5
— 1.5
— 250
0 ±350
5 8.7
0 700
——
— 200
—1
Unit
MHz
%
%
ns
ns
ps
ps
ns
ps
V/ns
ps
ms
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet IDT2309A-1HPGI.PDF ] | |
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