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PDF M68AF511A Data sheet ( Hoja de datos )

Número de pieza M68AF511A
Descripción 4 Mbit (512K x8) / 5V Asynchronous SRAM
Fabricantes ST Microelectronics 
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No Preview Available ! M68AF511A Hoja de datos, Descripción, Manual

M68AF511A
4 Mbit (512K x8), 5V Asynchronous SRAM
FEATURES SUMMARY
s SUPPLY VOLTAGE: 4.5 to 5.5V
s 512K x 8 bits SRAM with OUTPUT ENABLE
s EQUAL CYCLE and ACCESS TIMES: 55ns
s LOW STANDBY CURRENT
s LOW VCC DATA RETENTION: 2V
s TRI-STATE COMMON I/O
s LOW ACTIVE and STANDBY POWER
Figure 1. Packages
32
1
TSOP32 Type II (NC)
SO32 (MC)
October 2002
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1 page




M68AF511A pdf
Figure 4. Block Diagram
A18
A8
DQ7
DQ0
M68AF511A
ROW
DECODER
MEMORY
ARRAY
VCC
VSS
I/O CIRCUITS
COLUMN
DECODER
A0 A7
E
W
G
AI05916
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
Table 2. Absolute Maximum Ratings
Symbol
Parameter
IO (1)
Output Current
TA Ambient Operating Temperature
TSTG
Storage Temperature
VCC Supply Voltage
VIO (2)
Input or Output Voltage
PD Power Dissipation
Note: 1. One output at a time, not to exceed 1 second duration.
2. Up to a maximum operating VCC of 6.0V only.
plied. Exposure to Absolute Maximum Rating con-
ditions for periods greater than 1 sec may affect
device reliability. Refer also to the STMicroelec-
tronics SURE Program and other relevant quality
documents.
Value
20
–55 to 125
–65 to 150
–0.5 to 6.5
–0.5 to VCC +0.5
1
Unit
mA
°C
°C
V
V
W
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M68AF511A arduino
M68AF511A
Write Mode
The M68AF511A is in the Write mode whenever
the W and E pins are Low. Either the Chip Enable
input (E) or the Write Enable input (W) must be de-
asserted during Address transitions for subse-
quent write cycles. Write begins with the concur-
rence of Chip Enable being active with W low.
Therefore, address setup time is referenced to
Write Enable and Chip Enable as tAVWL and tAVEH
respectively, and is determined by the latter occur-
ring edge.
The Write cycle can be terminated by the earlier
rising edge of E, or W.
if the Output is enabled (E = Low and G = Low),
then W will return the outputs to high impedance
within tWLQZ of its falling edge. Care must be taken
to avoid bus contention in this type of operation.
Data input must be valid for tDVWH before the ris-
ing edge of Write Enable, or for tDVEH before the
rising edge of E, whichever occurs first, and re-
main valid for tWHDX or tEHDX.
Figure 10. Write Enable Controlled, Write AC Waveforms
A0-A18
E
W
DQ0-DQ7
tAVAV
VALID
tAVWH
tELWH
tWHAX
tAVWL
tWLWH
tWLQZ
DATA (1)
tWHDX
DATA INPUT
tDVWH
tWHQX
DATA (1)
AI05913
Note: 1. During this period DQ0-DQ7 are in output state and input signal should not be applied.
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