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PDF M66853J Data sheet ( Hoja de datos )

Número de pieza M66853J
Descripción SRAM TYPE FIFO MEMORY
Fabricantes Mitsubishi 
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MITSUBISHI <DIGITAL ASSP>
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
SRAM TYPE FIFO MEMORY
DESCRIPTION
M66850/851/852/853 are very high-speed and clock synchronous
FIFO(First-In,First-Out) memories fabricated by high-speed CMOS
technology.
These FIFOs are applicable for a data buffer as networks and
communications.
The write operation is controlled by a write clock pin(WCLK) and
two write enable pins(WEN1,WEN2).
Data present at the data input pins(D0-D8) is written into the
Synchronous FIFO on every rising write clock edge when the
device is enabled for writing.
The read operation is controlled by a read clock pin(RCLK) and
two read enable pins(REN1,REN2).
Data is read from the Synchronous FIFO on every rising read clock
edge when the device is enabled for reading. An output enable
pin(OE) controls the states of the data output pins(Q0-Q8).
MITSUBISHI FIFOs have four flags (EF,FF,PAE,PAF). The empty
flag EF and the full flag FF are fixed flags. The almost empty flag
PAE and the almost full flag PAF are programmable flags. The
programmable flag offset is initiated by the load pin(LD).
PIN CONFIGURATION (TOP VIEW)
D1 5
D0 6
PAF 7
PAE 8
GND 9
REN1 10
RCLK 11
REN2 12
OE 13
29 RS
28 WEN1
27 WCLK
26 WEN2/LD
25 VCC
24 Q8
23 Q7
22 Q6
21 Q5
Outline 32P0(M66850 – 853J)
FEATURES
• Memory configuration 64words x 9bits (M66850J/FP)
256words x 9bits (M66851J/FP)
512words x 9bits (M66852J/FP)
1024words x 9bits (M66853J/FP)
• Write and Read Clocks can be independent
• Advanced CMOS technology
• Programmable Almost-Empty and Almost-Full flags
• High-speed : 25ns cycle time
• Package Available :
32-pin Pastic Leaded Chip Carrier(PLCC)
32-pin Low profile Quad Flat Package(LQFP)
D1 1
D0 2
PAF 3
PAE 4
GND 5
REN1 6
RCLK 7
REN2 8
24 WEN1
23 WCLK
22 WEN2/LD
21 VCC
20 Q8
19 Q7
18 Q6
17 Q5
APPLICATION
• Data Buffer for networks communications.
Outline 32P6B(M66850 – 853FP)
BLOCK DIAGRAM
RS
WCLK
WEN1
WEN2
RESET
LOGIC
D0-D8
INPUT
REGISTER
OFFSET
REGISTER
LD
WRITE
CONTROL
WRITE
POINTER
MEMORY
ARRAY
READ
POINTER
READ
CONTROL
OUTPUT
REGISTER
RCLK
REN1
REN2
EF
OE
FLAG
LOGIC
PAE
PAF
FF
Q0-Q8
1

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M66853J pdf
MITSUBISHI <DIGITAL ASSP>
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
SRAM TYPE FIFO MEMORY
SWITCHING CHARACTERISTICS (Ta=0 – 70˚C, Vcc=5V±10%, GND=0V)
Symbol
tAC
tWFF
tREF
tPAF
tPAE
tOE
tOLZ
tOHZ
tRSF
Data Access Time
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Enable to Output in High-Z
Reset to Flag and Output Valid time
Parameter
Limits
Min. Typ. Max.
3 15
15
15
15
15
3 13
0
3 13
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING CONDITIONS (Ta=0 – 70˚C, Vcc=5V±10%, GND=0V)
Symbol
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tSKEW1
tSKEW2
Parameter
Clock Cycle Time
Clock Pulse Width HIGH
Clock Pulse Width LOW
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
Reset Setup Time
Reset Recovery Time
Skew time between Read Clock and Write Clock for Empty Flag and Full Flag
Skew time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full
Flag
Limits
Min. Typ. Max.
25
10
10
6
1
6
1
25
25
25
10
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND – 3.0V
3ns
1.5V
1.5V
See Figure 4
5.0V
1.1k
D.U.T.
680
30pF
Figure 4. Output Load
Including Test board and scope capacitances.
5

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M66853J arduino
Empty Flag Timing
WCLK
D0-D8
tDS
DATA WRITE1
WEN1
tENS tENH
tENS tENH
WEN2
(If Applicable)
RCLK
tFRL (1)
tSKEW1
tREF
EF
MITSUBISHI <DIGITAL ASSP>
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
SRAM TYPE FIFO MEMORY
tDS
DATA WRITE2
tENH
tENS
tREF
tENS tENH
tSKEW1
tFRL (1)
tREF
REN1
REN2
LOW
OE
tAC
Q0-Q8
DATA IN OUTPUT REGISTER
DATA READ
NOTE :
1. When tSKEW1minimum specification, tFRL maximum=tCLK+tSKEW1.
When tSKEW1minimum specification, tFRL maximum=2tCLK+tSKEW1 or tCLK+tSKEW1.
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