|
|
PDF M66307SP Data sheet ( Hoja de datos )
| Número de pieza | M66307SP | |
| Descripción | LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M66307SP (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
MIMTSITUSBUIBSHISIH〈DI 〈IDGIIGTAITLAALSASSPS〉P〉
M66307SP/FPM66307SP/FP
LINLEINSECASNCABNUFBFUEFRFEwRithw1it6h-B16ITBMITPMUPBUUBSUCSOCMOPMATPIABTLIBELIENPINUPTUSTS
DESCRIPTION
The M66307SP/FP is an integrated circuit consisting of a line buffer
with static memory, manufactured by the silicon gate CMOS pro-
cess, which satisfies A3-paper 400DPI requirements. It converts the
stored data from the 16-bit MPU bus into serial data and outputs it at
a transfer rate of up to 10Mbps synchronously with the external data
request clock or an arbitrary continuous clock.
FEATURES
• 16-bit MPU bus compatible
• Writing data via DMAC is possible
• 320-word (5,120-bit) static RAM
• Data output rate of up to 10Mbps
• Built-in function to add fixed data of a specified length at the be-
ginning of output data (Fixed data: Continuous High bit or Low bit
data)
• The output format can be selected between FIFO or LIFO.
• The output method can be selected from two:
(1) Synchronized with an arbitrary continuous clock (φ IN) on the
system side; the frequency of clock output (CLK/φ OUT) can
be divided by 1, 2, 4, 8, or 16.
(2) Synchronized with the data request clock (CLK IN) on the pe-
ripheral equipment side.
• Up to two devices can be cascaded.
(1) Toggle configuration
(2) 32-bit bus configuration
• High fan-out outputs (CLK/φ OUT, DATA OUT).
Io = ±24mA
(±4mA for INTR and DREQ
±8mA for BUSY/ORDY)
PIN CONFIGURATION (TOP VIEW)
D8 1
32 VCC(5V)
D9 2
31 D7
D10 3
30 D6
D11
DATA INPUTS
D12
D13
4
5
6
29 D5
28 D4
DATA INPUTS
27 D3
D14 7
26 D2
D15 8
25 D1
WRITE CONTROL
INPUT
WR
CHIP SELECT INPUT CS
COMMAND/DATA
CONTROL INPUT C/D
9
10
11
24 D0
DMA ACKNOWLEDGE
23 DACK
INPUT
22
DREQ
DMA REQUEST
OUTPUT
RESET INPUT RESET 12
21 EXD EXTENDED D INPUT
INTERROUUPTTPRUETQUESTINTR
13
20 TOG TOGGLE INPUT
CLOCK INPUT CLK/ φ IN
CLOCK ENABLE
INPUT
CLKE
14
15
19 CLK/ φ OUT CLOCK
OUTPUT
18 DATA OUT DATA OUTPUT
(0V)GND 16
17
BUSY/ORDY
BUSY/
OUTPUT
READY
Outline 32P4B
OUTPUT
32P2W-A
• The clock input (CLK/φ IN) contains a Schmitt trigger.
• The reset (RESET), Write (WR) and toggle input (TOG) contain
negative noise reduction circuits.
APPLICATION
Image-handling general OA equipment
BLOCK DIAGRAM
WR 9
CS 10
C/D 11
DACK 23
D0 24
D1 25
D2 26
D3 27
D4 28
D5 29
D6 30
D7 31
D8 1
D9 2
D10 3
D11 4
D12 5
D13 6
D14 7
D15 8
TOG 20
EXD 21
16
CLK/ φ IN 14
CLKE 15
Write
control
circuit
16
16
Command registers
Fixed data
length register
DREQ words register
Mode register
Expansion
control
circuit
GND VCC
16 32
Write/send
address
control
circuit
13
9
4
320 word
CMOS 16
SRAM
16
Clock
control
circuit
Frequency
divider
Clock signal
select circuit
RESET 12
Reset
control
circuit
9 Output
control
circuit
13
Output
control
circuit
Output
control
circuit
Output
control
circuit
22 DREQ
13 INTR
17 BUSY/ORDY
18 DATA OUT
19 CLK/ φ OUT
1
1 page  
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
PIN DESCRIPTIONS
Pin
Name
I/O
Function
D0~D15 Data inputs
Input Normally connected to a 16-bit bus.
WR Write control Input Data or command is stored to the M66307 at the Low to High transition. This signal is normally
input
connected to the write control signal of the control bus.
CS
Chip select
Input When Low, this signal allows data or command to be stored from the MPU to the M66307. It is normally
input
connected to the address bus directly or via a decoder. When this signal is High, the MPU cannot
access the M66307.
DACK
DMA
acknowledge
input
Input
When Low, this signal allows data to be stored by DMA transfer. It is normally connected to the DMA
acknowledge output (DACK) of the DMA controller.For systems where DMA transfer is not used, this
pin must be pulled-up to VCC.
C/D
Command/
Input This signal discriminates whether the information on the data bus when the MPU accessed the M66307
data control
is command or data. When High, the signal indicates that the information is a command; when Low, it
input
indicates data. It is normally connected to the address bus directly or via a decoder.
RESET Reset input
Input
When Low, this signal initializes the command registers and various circuits of the M66307. As a result,
all active Low output signals are set High; clock outputs (CLK, φ OUT) are set High; data output (DATA
OUT) is set Low.
DREQ
DMA request
output
Output
This signal requests DMA cycles. When data store by DMA cycle is defined in the initialization and the
number of DMA transfer words is specified, this output is set Low when the M66307 is set into the write
mode.
When the set number of DMA cycles are completed, it returns High.
INTR
Interrupt
Output This signal requests an interrupt to the MPU when the written data is sent out (Low output). This
request output
request is cleared by MPU access or toggle input(TOG) [when extended toggle is used] (High output).
BUSY/
ORDY
BUSY/
OUTPUT
READY
output
Output
When Low, this signal informs the MPU that no commands other than STOP can be set to the M66307,
and informs the peripheral equipment that the M66307 is sending data.
When the M66307 is in the send mode, this signal is set Low; when transmission is completed, it
returns High.
CLKE
Clock enable Input When Low, this signal enables clock input (CLK/φ IN); when High, it disables the clock input. When
input
clock input is φ IN, CLKE is invalid so that this pin must be pulled-up to VCC or pulled-down to GND.
CLK/φ IN Clock input
Input
CLK IN is generally used as data request clock from peripheral equipment; φ IN is generally used as
continuous clock on the system side. Selection between CLK IN and φ IN is specified by the initialization
command. Select CLK IN when the data output timing must be matched to the timing of the peripheral
equipment. Select φ IN when the timing need not be matched and data can be sent at a stroke using the
clock from the system. φ IN can be divided into one of five smaller frequencies when the peripheral
equipment is slow to read data. (Note: The continuous clock of φ IN may not necessarily be the system
clock.)
TOG
Toggle input
Input
This signal can only be valid when extended toggle is used (using two M66307s) and CLK IN is
selected for clock input. This input sets the write and send modes. Each time this signal is set Low, the
IC in the write mode is reversed to the send mode and the IC in the send mode is reversed to the write
mode. It is impossible to control mode inversion with this function and operation mode setting
command together.
DATA
OUT
CLK/
φ OUT
EXD
Data output
Output The data stored in the internal memory or fixed data is serially output synchronously with clock input
(CLK/φ IN) according to the settings of output format (LSB/MSB, LIFO/FIFO).
Clock output
Extended D
input
Output Peripheral devices take in data with the “rise” of clock pulses.
Input
This signal is used for an extended system using two M66307s. Connect the EXD of the master IC to
the DATA OUT pin of the slave IC. The EXD of the slave IC must be pulled-up to VCC. (See the
application example.) For normal use, pull up EXD to VCC or pull down it to GND.
5
5 Page 
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Send mode set
CS
C/D
DACK
WR
D0~D15
CLK IN
CLK/φ OUT
DATA OUT
BUSY/ORDY
INTR
DREQ
12
Fixed data
Write mode set
Note : Y=(n+1)+16×N
n+1 n+2 n+3 n+4 Y–3 Y–2 Y–1 Y (Y+1) (Y+2)
DOF DOE
(Note)
DN3 DN2 DN DN0 (Fixed data)
Fixed data
Note : DATA OUT outputs fixed data with CLK IN of (n+1)+(16×N)+1 or more.
: N:Transfer words; n:fixed beginning data length (register set value)
: Dij: i=transfer words (0-N); j=bits (0-F)
Fig. 9 Send timing of M66307 (CLK IN, with fixed begnning data output, FIFO, MSB)
WR
D0~D15
φ IN
CLK/φ OUT
DATA OUT
BUSY/ORDY
INTR
Send mode set
Fixed data
DOF DOE
DN3 DN2 DN1 DN0
Note : The same input/output and conditions as in Figure 8 are not shown here.
Write mode set
Fixed data
Fig. 10 Send timing of M66307 (φ IN without fixed data output, FIFO, MSB)
Send mode set
WR
D0~D15
CLK IN
12 3
CLK/φ OUT
DATA OUT
Fixed data
Write mode set
N×16–2 N×16–1 N×16 N×16+1
(Note)
(Fixed data)
Fixed data
FIFO, MSB
DOF DOE DOD
DN3 DN2 DN1 DN0
Output formats
FIFO, LSB
LIFO, MSB
DOO DO1 DO2
DNF DNE DND
DNC DND DNE DNF
D03 D02 D01 D00
LIFO, LSB
DN0 DN1 DN2
DOC DOD DOE DOF
Note : The same input/output and conditions as in Figure 8 are not shown here.
Fig. 11 Send timing of M66307 (CLK IN, without fixed data output)
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet M66307SP.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M66307SP | LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS | Mitsubishi |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |