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PDF M66282FP Data sheet ( Hoja de datos )

Número de pieza M66282FP
Descripción 8192 x 8-BIT LINE MEMORY
Fabricantes Mitsubishi 
Logotipo Mitsubishi Logotipo



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No Preview Available ! M66282FP Hoja de datos, Descripción, Manual

MITSUBISHI <DIGITAL ASSP>
M66282FP
8192 x 8-BIT LINE MEMORY
DESCRIPTION
The M66282FP is high speed line memory that uses high
performance silicon gate CMOS process technology and adopts
the FIFO (First In First Out) structure consisting of 8192 words x 8
bits.
The M66282FP, performing reading and writing operations at
different cycles independently and asynchronously, is optimal for
buffer memory to be used between equipment of different data
processing speeds.
FEATURES
• Memory configuration 8192 words x 8 bits (dynamic memory)
• High speed cycle
25 ns (Min.)
• High speed access
18 ns (Max.)
• Output hold
3 ns (Min.)
• Reading and writing operations can be completely carried out
independently and asynchronously.
• Variable length delay bit
• Input/output
TTL direct connection allowable
• Output
3 states
APPLICATION
• Digital copying machine, laser beam printer, high speed facsimile,
etc.
FUNCTION
When write enable input WEB is set to "L", the contents of data
inputs D0 to D7 are read in synchronization with a rising edge of
write lock input WCK to perform writing operation. When this is the
case,the write address counter is also incremented simultaneously.
When WEB is set to "H", the writing operation is inhibited and the
write address counter stops.
When write reset input WRESB is set to "L", the write address
counter is initialized.
When read enable input REB is set to "L", the contents of memory
are output to data outputs Q0 to Q7 in synchronization with a rising
edge of read clock input RCK to perform reading operation. When
this is the case, the read address counter is incremented
simultaneously.
When REB is set to "H", the reading operation is inhibited and the
read address counter stops. The outputs are placed in a high
impedance state.
When read reset input RRESB is set to "L", the read address
counter is initialized.
PIN CONFIGURATION (TOP VIEW)
Q0 1
Q1 2
DATA OUTPUT
Q2 3
Q3
READ ENABLE
INPUT
REB
READ RESET
INPUT
RRESB
4
5
6
READ CLOCK
INPUT
GND 7
RCK 8
Q4 9
Q5 10
DATA OUTPUT
Q6 11
Q7 12
24 D0
23 D1
DATA INPUT
22 D2
21 D3
20 WEB
WRITE ENABLE
INPUT
19
WRESB
WRITE RESET
INPUT
18 VCC
17 WCK
WRITE CLOCK
INPUT
16 D4
15 D5
DATA INPUT
14 D6
13 D7
Outline 24P2Q-A(SSOP)
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M66282FP pdf
SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT
MITSUBISHI <DIGITAL ASSP>
M66282FP
8192 x 8-BIT LINE MEMORY
VCC
Qn
CL = 30pF : tAC, tOH
RL=1K
SW1
Qn
RL=1K
SW2
CL = 5pF : tOEN, tODIS
Input pulse level
: 0 – 3V
Input pulse up/down time : 3 ns
Judging voltage Input
: 1.3V
Output
: 1.3V(However, tODIS(LZ) is judged with 10% of the
output amplitude, while tODIS(HZ) is judged with
90% of the output amplitude.)
Load capacitance CL includes the floating capacity of connected lines and input
capacitance of probe.
Item
tODIS(LZ)
tODIS(HZ)
tOEN(ZL)
tOEN(ZH)
SW1
Close
Open
Close
Open
SW2
Open
Close
Open
Close
tODIS and tOEN measurement condition
RCK
1.3V
REB
Qn
Qn
tODIS(HZ)
90%
tODIS(LZ)
10%
1.3V
3V
GND
tOEN(ZH)
1.3V
tOEN(ZL)
3V
GND
VOH
1.3V
VOL
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M66282FP arduino
MITSUBISHI <DIGITAL ASSP>
M66282FP
8192 x 8-BIT LINE MEMORY
Reading shortest n-cycle write data "n"
(Reading side n-1 cycle starts after the end of writing side n-1 cycle.)
When the reading side n-1 cycle starts before the end of the writing side n+1 cycle, output Qn of n cycle is made invalid.
In the following diagram, reading operation of n-1 cycle is invalid.
WCK
Dn
RCK
Qn
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
(n) (n+1)
n-2 cycle
(n+2)
n-1 cycle
(n+3)
n cycle
invalid
(n)
Reading longest n-cycle write data "n": 1 line delay
(When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts.)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each
other.
WCK
n cycle <1>*
0 cycle <2>*
n cycle <2>*
Dn (n-1)<1>*
(n)<1>*
RCK
n cycle <0>*
Qn (n-1)<0>*
(n)<0>*
(0)<2>*
0 cycle <1>*
(n-1)<2>*
(n)<2>*
n cycle <1>*
(0)<1>*
(n-1)<1>*
(n)<1>*
<0>*, <1>* and <2>* indicate value of lines.
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