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PDF M66273FP Data sheet ( Hoja de datos )

Número de pieza M66273FP
Descripción LCD CONTROLLER with VRAM
Fabricantes Mitsubishi 
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No Preview Available ! M66273FP Hoja de datos, Descripción, Manual

MITSUBISHI <DIGITAL ASSP>
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
DESCRIPTION
The M66273 is a graphic display-only controller for dot matrix type STN-
LCD which is used widely for OA equipment, PDA, amusement
equipment, etc.
The M66273 is an advanced product from the M66272 at the point of MPU
interface and timing specifications. This LCD display functions are the
same with the M66272.
It is capable of displaying six types of LCD by combining the panel
configuration(single or dual scan), LCD display function(binary or gray
scale), LCD display data bus width(4 or 8 bit).
Panel
configuration
Single scan
Dual scan
Binary/
gray scale
LCD
display
data
Displayable LCD size
Binary
4bit
8bit
Equivalent to 640 x 240
Gray scale
4bit
8bit
Equivalent to 320 x 240
Binary
4bit
Equivalent to 320 x 240 x 2 screens
Gray scale 4bit Equivalent to 320 x 120 x 2 screens
The M66273 can support the reflective color type LCD (ECB : Electrically
Controlled Birefringence).
The IC has a built-in 19200-byte VRAM as a display data memory. All of
the VRAM addresses are externally opened. Direct addressing of display
data can be performed from MPU, thus display data processing such as
drawing can be efficiently carried out.
The built-in arbiter circuit(cycle steal system) which gives priority to
display access allows timing-free access from MPU to VRAM, preventing
display screen distortion.
The IC provides has a function for LCD module built-in system by
lessening connect pins between the MPU and the IC.
FEATURES
· Display memory
·Built-in 19200-byte(153.6-Kbit) VRAM(Equivalent to 640 x 240 dots x 1
screen, 320 x 240 dots x 2 screens)
· All addresses of built-in VRAM are externally opened.
· Displayable LCD
· Binary display
Monochrome STN-LCD of up to 153600 dots(equivalent to 1/2
VGA)
· 4 gray scale display
Monochrome STN-LCD of up to 76800 dots(equivalent to 1/4 VGA)
Reflective color STN-LCD of up to 76800 dots (equivalent to 1/4
VGA)
· Interface with MPU
· Capability of switching the interface with two-way 8/16-bit MPU
· Provides WAIT output pin(WAIT output when access from MPU to
VRAM is gained)
· Capability of controlling BHE or LWR/HWR at the interface with a
16-bit MPU
· Interface with LCD
· LCD display data bus is a 4-bit or 8-bit parallel output.
· 4 kinds of control signals: CP, LP, FLM and M
· Display functions
· Graphic display only
· Binary or 4 gray scale display(gray scale palette is used to set
pseudo medium 2 gray scale.)
· Reflective color(ECB) uses a gray scale function.
· Vertical scrolling is allowed within memory range.
· Additional function for LCD module built-in system
· Capability of interfacing with two-way 8/16-bit MPU(16-bit MPU
byte access is not allowed.)
· Access from MPU to VRAM is gained via the I/O register.
· 5V or 3V single power supply
APPLICATION
PPC/FAX operation panel, display/operation panel of other OA
equipment, multifunction/public telephone
· PDA/electronic notebook/information terminal, portable terminal
· Game, Amusements, Kids computer, etc.
PIN CONFIGURATION
(TOP VIEW)
VSS
DISPLAY DATA TRANSFER CLOCK CP
DISPLAY DATA LATCH PULSE LP
FIRST LINE MARKER SIGNAL FLM
VD<0>
VD<1>
VD<2>
VD<3>
LCD DISPLAY DATA BUS
VD<4>
VD<5>
VD<6>
VD<7>
VDD
N. C
N. C
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
M66273FP
40 VS S
39 N.C
38 N.C
37 N.C
36 CSE
CYCLE STEAL
35 VS S
ENABLE
34 VDD
33 WAITCNT WAIT CONTROL
32 A<14>
31 A<13>
30 A<12>
29 A<11>
28 A<10>
27 A<9>
MPU ADDRESS
BUS
26 A<8>
25 VS S
Outline 80P6N-A
N.C : No Connection
1

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M66273FP pdf
Ver.3.1 Dec,1999
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
OUTLINE
The M66273 is a graphic display only controller for displaying a dot
matrix type STN-LCD.
· LCD display mode
It is capable of displaying six types of LCD by combining the panel
configuration, binary/gray scale, LCD display data bus width.
Display Panel
Binary/ LCD display Displayable LCD
mode configuration gray scale data
size
1 4bit Equivalent to 640
2
Single
Binary
8bit x 240
3
scan
Gray scale
4bit
Equivalent to 320
4 8bit x 240
5
Dual Binary
4bit
Equivalent to 320 x
240 x 2 screens
6
scan Gray scale
4bit
Equivalent to 320 x
120 x 2 screens
· Control register
When accessing the control register from MPU, use pins IOCS,
LWR, RD, A<7:0> and D<7:0>, or MCS, LWR, RD,A<14:0> and
D<7:0> (However, use D<15:0> only when 16-bit MPU controls the
LCD module built-in support function.)
Refer to Table-1, setting of control input.
The IC contains the following registers as control registers.
Operation control
R1 to R11
Supporting LCD module built-in type R12 to 14 or R15 to 16
Gray scale pattern table
R17 to R80
· VRAM
This IC has a built-in 19200-byte VRAM which is equivalent to two
screens of 320 x 240 dots LCD.
When accessing VRAM from MPU, use pins MCS, HWR, LWR,
RD, BHE, A<14:0> and D<15:0>.
Use of MPUSEL input can support both 8/16 bit MPU.
Refer to table-2 to 6, VRAM specifications for 8/16 bit MPU and input
setting in access.
The VRAM address settable range is restricted depending on the
panel configuration, as follows.
VRAM address settable range
· When single scan mode
·A<14:0>=0000 to 4AFFH --- 19200 byte
0000H
VRAM
4AFFH
· When dual scan mode
·For the 1st screen --- A<14:0>=0000 to 257F H --- 9600 byte
·For the 2nd screen --- A<14:0>=2580 to 4AFFH --- 9600 byte
0000H
VRAM for the 1st screen
257FH
2580H
VRAM for the 2nd screen
4AFFH
· Cycle steal system
Cycle steal system is interact method of transforming display data for
LCD from VRAM and accessing VRAM from MPU on the basic
cycle (MAINCLK) of internal operation.
Basic timing is two clocks of MAINCLK, and assign first clock to the
access from MPU to VRAM and second clock to the transfer of
display data from VRAM to LCD.
In accessing VRAM from MPU, output WAIT. In case of fixed
WAITCNT input, change WAIT to "L" at the timing of the falling edge
of overlapping with MCS and RD or LWR / HWR,and in case of
using WAITCNT input, change WAIT to "L" at the timing of the falling
edge of WAITCNT on MCS="L", And return to "H" at synchronizing
with rising edge of M PUCLK after internal processing.
For the cycle steal system, this IC provides a cycle steal control
function to improve data transfer efficiency in a line. This func-tion
gains access with the cycle steal system by taking WAIT for MPU
during the display term with necessity for the display data transfer
from built-in VRAM to LCD. On the other side, it does not output
WAIT for keeping throughput of MPU during horizontal synchronous
term (idle running term) with no necessity for the display data
transfer from VRAM to LCD side.
In detail,refer to "Description of cycle steal".
· Output to LCD side
LCD display data VD<7:0> is output in parallel per 4 bits or 8 bits in
synchronization with the rising edge of CP.
Pin VD<n:0> differs depending on the display mode.
Single scan
4-bit transfer
8-bit transfer
VD<3:0>
VD<7:0>
Dual scan
4-bit transfer
VD<7:4>
VD<3:0>
Display mode 1 3
24
56
When display data for a line has been sent, LP outputs data in
synchronization with the falling edge of MAINCLK.
The IC enables adjustment to an optimum value of the frame
frequency as requested from the LCD PANEL side by adjusting pulse
width of LP with the LPW register value.
FLM is output when the display data for the first line has been sent.
M output is an LCD alternating signal for driving LCD with alternating
current.
M output cycles can be set in lines with the M output cycle variable
register and is available to prevent LCD from deterioration.
· Gray scale display function
Gray scale display can assign 2-bit VRAM data to a picture element
of LCD display to show the display density at four levels.
Gray scale display pattern tables 0 and 1 (4 x 4 matrix x 16 patterns x
2 medium gray scale), consisting of SRAM of 64 bytes in total, can
set any gray scale display pattern.
In detail,refer to "Description of gray scale function".
· Application to reflective color type LCD
The above gradation display function is available to control about four
display colors on the reflective color type LCD with ECB (Electrically
Controlled Birefringence).
5

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M66273FP arduino
MITSUBISHI <DIGITAL ASSP>
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
[R7, R8] 1st screen display start address
Address R/W
Function
SA1H
SA1L
0C H
(SA1L)
D7 D6 to D0 D7 to D0
00H 00H
00H 02H
R/W
00H 04H
1st screen display start
address
0000H
0002H
0004H
0EH
(SA1H)
4AH FEH
4AFEH
·Sets the 1st screen display
start address.
·The display start address is
determined by writing data
into SA1H.
·Reading SA1H outputs "0" to
D7.
·Resetting sets "0000H".
Restriction
Reset
·At the display start add-ress,
even addresses can only
be set.
· For single scan;
0000H to 4AFEH
· For dual scan;
Sets 0000H to 257EH.
Settings except for the
above must not be made.
·To modify the display start
address, be sure to
respecify in order of SA1L-
SA1H even when only
SA1L is modified.
00H
00H
[R9, R10] 2nd screen display start address
Address R/W
Function
SA2H
SA2L
10H
(SA2L)
D7 D6 to D0 D7 to D0
25H 80H
25H 82H
R/W
25H 84H
2nd screen display start
address
2580H
2582H
2584H
12H
(SA2H)
4AH FEH
4AFEH
·Used for dual scan mode
only to set the 2nd
screen display start
address.
·The display start address is
determined by writing data
into SA2H.
·Reading SA2H outputs "0" to
D7.
·Resetting sets "2580H".
Restriction
Reset
·At the displaystart add-
ress, onlyeven addre-
sses can be set, and;
·Can set 2580H to 4AFEH.
Settings except for the
above must not be
made.
·To modify the display start
address, be sure to
respecify in order of
SA2L - SA2H even when
only SA2L is modified.
80H
25H
[R11] M output cycle variable
Address R/W
Function
MT
D7 to D0
Output cycle of M signal
00H Makes toggle change every frame.
14H W 01H Makes toggle change every line (=1LP).
02H Makes toggle change every 2 lines.
FFH Makes toggle change every 255 lines.
·Sets the output cycle of M signal
output from the M terminal.
With MT=01H, for example, M sig-
nal repeatedly reverses (toggles)
every line.
·Resetting sets "00H".
·It is recommended to set this
register to an optimum value ac-
cording to the LCD specification.
Restriction
Reset
00H
11

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