PDF M66257 Data sheet ( Hoja de datos )

Número de pieza	M66257
Descripción	5120 x 8-BIT x 2 LINE MEMORY (FIFO)
Fabricantes	Mitsubishi
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No Preview Available ! MITMSITUSBUISBHISI H〈DI I〈GDIITGAITLAALSASSPS〉 P〉 M662M56672F57PFP DESCRIPTION The M66257FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit double con- figuration which uses high-performance silicon gate CMOS process technology. It allows simultaneous output of 1-line delay data and 2-line delay data, and is most suitable for data correction over mul- tiple lines. It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between de- vices with different data processing throughput. FEATURES • Memory configuration of 5120 words × 8 bits × 2 (dynamic memory) • High-speed cycle ............................................. 25ns (Min.) • High-speed access ......................................... 18ns (Max.) • Output hold ........................................................ 3ns (Min.) • Fully independent, asynchronous write and read operations • Output .................................................................... 3 states • Q00 to Q07 ........................................................ 1-line delay • Q10 to Q17 ........................................................ 2-line delay APPLICATION Digital photocopiers, high-speed facsimile, laser beam print- ers. 5125012×08×-B8IT-B×IT2×L2INLEINMEEMMEOMROYR(FYIF(FOIF) O) PIN CONFIGURATION (TOP VIEW) GND 1 Q00 ← 2 Q01 ← 3 Q02 ← 4 Q03 ← 5 Q04 ← 6 Q05 ← 7 Q06 ← 8 Q07 ← 9 DATA OUTPUT Q10 ← 10 Q11 ← 11 Q12 ← 12 Q13 ← 13 Q14 ← 14 Q15 ← 15 Q16 ← 16 Q17 ← 17 VCC 18 36 VCC 35 ← RE READ ENABLE INPUT 34 ← RRES READ RESET INPUT 33 ← RCK READ CLOCK INPUT 32 ← WE WRITE ENABLE INPUT 31 ← WRES WRITE RESET INPUT 30 ← WCK WRITE CLOCK INPUT 29 GND 28 VCC 27 ← D0 26 ← D1 25 ← D2 24 ← D3 23 ← D4 DATA INPUT 22 ← D5 21 ← D6 20 ← D7 19 GND Outline 36P2R-A BLOCK DIAGRAM DATA INPUT D0 ~ D7 27 26 25 24 23 22 21 20 INPUT BUFFER DATA OUTPUT Q00 ~ Q07 DATA OUTPUT Q10 ~ Q17 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 OUTPUT BUFFER WRITE ENABLE INPUT WE 32 WRITE RESET INPUT WRES 31 WRITE CLOCK INPUT WCK 30 VCC 18 VCC 28 VCC 36 MEMORY ARRAY OF 5120-WORD × 8-BIT × 2 CONFIGURATION 1-LINE DELAY DATA ONLY MEMORY/ 2-LINE DELAY DATA ONLY MEMORY 35 RE READ ENABLE INPUT READ 34 RRES RESET INPUT READ 33 RCK CLOCK INPUT 1 GND 19 GND 29 GND 1 1 page TEST CIRCUIT Qn CL=30pF : tAC, tOH MITSUBISHI 〈DIGITAL ASSP〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO) VCC RL=1kΩ SW1 Qn SW2 RL=1kΩ CL=5pF : tOEN, tODIS Input pulse level : 0 ~ 3V Input pulse rise/fall time : 3ns Decision voltage input : 1.3V Decision voltage output : 1.3V (However, tODIS(LZ) is 10% of output amplitude and tODIS(HZ) is 90% of that for decision). The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe. Parameter tODIS(LZ) tODIS(HZ) tOEN(ZL) tOEN(ZH) SW1 Closed Open Closed Open SW2 Open Closed Open Closed tODIS/tOEN TEST CONDITION RCK 1.3V RE tODIS(HZ) Q0n 90% Q1n tODIS(LZ) Q0n Q1n 10% 1.3V tOEN(ZH) 1.3V tOEN(ZL) 1.3V 3V GND 3V GND VOH VOL 5 5 Page

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