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PDF M66256FP Data sheet ( Hoja de datos )
| Número de pieza | M66256FP | |
| Descripción | 5120 x 8-BIT LINE MEMORY (FIFO) | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITMSITUSBUISBHISI H〈DI I〈GDIITGAITLAALSASSPS〉 P〉
M662M56662F56PFP
DESCRIPTION
The M66256FP is a high-speed line memory with a FIFO
(First In First Out) structure of 5120-word × 8-bit configuration
which uses high-performance silicon gate CMOS process
technology.
It has separate clock, enable and reset signals for write and
read, and is most suitable as a buffer memory between de-
vices with different data processing throughput.
FEATURES
• Memory configuration ........................................................
............................. 5120 words × 8-bits (dynamic memory)
• High-speed cycle ............................................. 25ns (Min.)
• High-speed access ......................................... 18ns (Max.)
• Output hold ........................................................ 3ns (Min.)
• Fully independent, asynchronous write and read operations
• Variable length delay bit
• Output .................................................................... 3 states
APPLICATION
Digital photocopiers, high-speed facsimile, laser beam print-
ers.
5125012×08×-B8IT-BLITINLEINMEEMMEOMROYR(FYIF(FOIF) O)
PIN CONFIGURATION (TOP VIEW)
Q0 ← 1
Q1 ← 2
DATA OUTPUT
Q2 ← 3
Q3 ← 4
READ ENABLE INPUT RE → 5
READ RESET INPUT RRES→ 6
GND 7
READ CLOCK INPUT RCK → 8
Q4 ← 9
Q5 ← 10
DATA OUTPUT
Q6 ← 11
Q7 ← 12
24 ← D0
23 ← D1
DATA INPUT
22 ← D2
21 ← D3
20 ← WE WRITE ENABLE INPUT
19 ← WRES WRITE RESET INPUT
18 VCC
17 ← WCK WRITE CLOCK INPUT
16 ← D4
15 ← D5
DATA INPUT
14 ← D6
13 ← D7
Outline 24P2U-A
BLOCK DIAGRAM
WRITE
ENABLE INPUT WE 20
WRITE
RESET INPUTWRES 19
WRITE
CLOCK INPUT WCK 17
VCC 18
DATA INPUT
D0 ~ D7
13 14 15 16 21 22 23 24
INPUT BUFFER
DATA OUTPUT
Q0 ~ Q7
1 2 3 4 9 10 11 12
OUTPUT BUFFER
MEMORY ARRAY OF
5120-WORD × 8-BIT
CONFIGURATION
READ
5 RE ENABLE INPUT
READ
6 RRES RESET INPUT
READ
8 RCK CLOCK INPUT
7 GND
1
1 page  
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
OPERATING TIMING
• Write cycle
WCK
Cycle n
Cycle n+1
Cycle n+2
tWCK
tWCKH tWCKL tWEH tNWES
5120 × 8-BIT LINE MEMORY (FIFO)
Disable cycle
Cycle n+3
Cycle n+4
tNWEH tWES
WE
tDS tDH
tDS tDH
Dn
(n)
( n+1)
(n+2)
(n+3)
(n+4)
WRES = “H”
• Write reset cycle
WCK
WRES
Dn
Cycle n–1
Cycle n
Reset cycle
tWCK
tNRESH tRESS
tDS tDH
tDS tDH
(n–1)
(n)
Cycle 0
Cycle 1
Cycle 2
tRESH tNRESS
(0) (1) (2)
WE = “L”
5
5 Page 
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
APPLICATION EXAMPLE
Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction.
B
Line (n+1)
image data
M66256
D0 Q0
D9 Q9
1-line
delay
N
Line n image data
×2
M66256
D0 Q0
D9 Q9
A
Line (n–1)
image data
1-line
delay
×K
Corrected
image data
Primary scanning
direction
A
N
B
Line (n–1)
Line n
Line (n+1)
N' = N+K {(N–A)+(N–B)}
= N+K {2N–(A+B)}
K : Laplacean coefficient
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet M66256FP.PDF ] | |
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