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PDF M66255FP Data sheet ( Hoja de datos )
| Número de pieza | M66255FP | |
| Descripción | 8192 x 10-BIT LINE MEMORY (FIFO) | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITMSITUSBUISBHISI H〈DI I〈GDIITGAITLAALSASSPS〉 P〉
M662M56652F55PFP
DESCRIPTION
The M66255FP is a high-speed line memory with a FIFO
(First In First Out) structure of 8192-word × 10-bit configura-
tion which uses high-performance silicon gate CMOS pro-
cess technology.
It has separate clock, enable and reset signals for write and
read, and is most suitable as a buffer memory between de-
vices with different data processing throughput.
FEATURES
• Memory configuration of 8192 words × 10 bits (dynamic
memory)
• High-speed cycle ............................................. 30ns (Min.)
• High-speed access ......................................... 25ns (Max.)
• Output hold ........................................................ 5ns (Min.)
• Fully independent, asynchronous write and read operations
• Variable length delay bit
• Output .................................................................... 3 states
APPLICATION
Digital photocopiers, high-speed facsimile, laser beam print-
ers.
8192 × 10-BIT LINE MEMORY (FIFO)
8192 × 10-BIT LINE MEMORY (FIFO)
PIN CONFIGURATION (TOP VIEW)
Q0 ← 1
Q1 ← 2
DATA OUTPUT Q2 ← 3
Q3 ← 4
Q4 ← 5
READ ENABLE INPUT RE → 6
READ RESET INPUT RRES → 7
GND 8
READ CLOCK INPUT RCK → 9
Q5 ← 10
Q6 ← 11
DATA OUTPUT Q7 ← 12
Q8 ← 13
Q9 ← 14
28 ← D0
27 ← D1
26 ← D2 DATA INPUT
25 ← D3
24 ← D4
23 ← WE WRITE ENABLE INPUT
22 ← WRES WRITE RESET INPUT
21 VCC
20 ← WCK WRITE CLOCK INPUT
19 ← D5
18 ← D6
17 ← D7 DATA INPUT
16 ← D8
15 ← D9
Outline 28P2W-C
BLOCK DIAGRAM
WRITE
ENABLE INPUT WE 23
WRITE
RESET INPUT WRES 22
WRITE
CLOCK INPUT WCK 20
VCC 21
DATA INPUT
D0 ~ D9
15 16 17 18 19 24 25 26 27 28
INPUT BUFFER
DATA OUTPUT
Q0 ~ Q9
1 2 3 4 5 10 11 12 13 14
OUTPUT BUFFER
MEMORY ARRAY OF
8192-WORD × 10-BIT
CONFIGURATION
6 RE
READ
ENABLE INPUT
READ
7 RRES RESET INPUT
READ
9 RCK CLOCK INPUT
8 GND
1
1 page  
MITSUBISHI 〈DIGITAL ASSP〉
M66255FP
OPERATING TIMING
• Write cycle
WCK
Cycle n
Cycle n+1
Cycle n+2
tWCK
tWCKH tWCKL tWEH tNWES
8192 × 10-BIT LINE MEMORY (FIFO)
Disable cycle
Cycle n+3
Cycle n+4
tNWEH tWES
WE
tDS tDH
tDS tDH
Dn
(n)
( n+1)
(n+2)
(n+3)
(n+4)
WRES = “H”
• Write reset cycle
WCK
WRES
Dn
Cycle n–1
Cycle n
Reset cycle
tWCK
tNRESH tRESS
tDS tDH
tDS tDH
(n–1)
(n)
Cycle 0
Cycle 1
Cycle 2
tRESH tNRESS
(0) (1) (2)
WE = “L”
5
5 Page 
MITSUBISHI 〈DIGITAL ASSP〉
M66255FP
8192 × 10-BIT LINE MEMORY (FIFO)
APPLICATION EXAMPLE
Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction.
B
Line (n+1)
image data
M66255
D0 Q0
D7 Q7
1-line
delay
N
Line n image data
×2
M66255
D0 Q0
D7 Q7
A
Line (n–1)
image data
1-line
delay
×K
Corrected
image data
Primary scanning
direction
A
N
B
Line (n–1)
Line n
Line (n+1)
N' = N+K {(N–A)+(N–B)}
= N+K {2N–(A+B)}
K : Laplacean coefficient
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet M66255FP.PDF ] | |
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