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PDF M66244FP Data sheet ( Hoja de datos )
| Número de pieza | M66244FP | |
| Descripción | High Speed Monolithic Pulse Width Modulator | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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PRELIMINARY DATA SHEET
MITSUBISHI <DIGITAL ASSP>
M66244FP
June 1998 Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
NOTE:This is not final specification. Some parametric limits are subject to change
DESCRIPTION
The M66244FP is a high-speed digitally programmable pulse width modulator (PWM) which
uses high-performance silicon gate CMOS process technology.Output pulse width is
proportional to a 6-bit DATA input value. Two additional CONTROL inputs determine if the
pulse is placed at the beginning , middle ,or end of the clock period. Pulse width and
placement can be changed every clock cycle up to 72MHz.
FEATURES
• Frequency 45MHz to 72MHz
• 6 bit Resolution
• Center, Leading, Trailing Edge Modulation
• Single 3.3V Operation
• JTAG (IEEE Standard 1149.1Test Port)
APPLICATIONS
• Laser Printers
Gray Scale Capability
Resolution Enhancement
• Copiers
• Optical Disk Drives
• Precision Pulse Placement
PIN CONFIGURATION (TOP VIEW)
TEST PIN
(JTAG)
TEST CLOCK INPUT
TEST MODE INPUT
TEST RESET INPUT
TCK
TMS
TRST
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
FREQUENCY
RANGE SET INPUT
FRANGE1
FRANGE2
LINE SIGNAL INPUT
PULSE MODE
CONTROL
INPUT
LS
SEM/DEM
LEM/TEM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36 TDI TEST DATA INPUT
TEST PIN
35 TDO TEST DATA OUTPUT (JTAG)
34 GND
33 CLK CLOCK INPUT
32 VDD
31 RESET RESET INPUT
30 SET SET INPUT
29 VDD
28 GND
27 PWMOUT
26 VDD
25 GND
24 D0(LSB)
23 D1
22 D2
21 D3
DATA BUS
INPUT
20 D4
19 D5(MSB)
Outline 36P2R
C 1998 MITSUBISHI ELECTRIC CORPORATION
(1/15)
1 page  
June 1998 Ver.8.0.0
MITSUBISHI <DIGITAL ASSP>
M66244FP
High Speed Monolithic Pulse Width Modulator
OPERATING TIMING BETWEEN POWER ON TO NORMAL OPERATION
After Power on, it needs following oerations before start normal operation.
(1) Set the value of FRANGE1 and FRANGE2 depends on operation ferequency. (Refer to page 9)
(2) Input CLK same as normal operarion frequency.
(3) Reset operarion using RESET (31pin) and TRST (3pin) .
(reset to initial state of internal logic and BSR)
(4) CLK continue to input during 100msec.
Power ON
reset cycle
RESET
tsu(RESET)
set up period
of internal circuit
100msec
th(RESET)
normal operation
period
TRST
CLK
FRANGE1
FRANGE2
D<5:0>
SEM/DEM
Fixed value determined page9
Fixed value determined page9
n n+1 n+2
n n+1 n+2
LEM/TEM
PWMOUT
Note: The reset cycle requires a minimum of two cycles.
C 1998 MITSUBISHI ELECTRIC CORPORATION (5/15)
n n+1 n+2
td(PWM)
N cycle
output
n
5 Page 
June 1998 Ver.8.0.0
TEST CIRCUIT DESCRIPTION (JTAG)
MITSUBISHI <DIGITAL ASSP>
M66244FP
High Speed Monolithic Pulse Width Modulator
GENERAL DESCRIPTION
The Test Access Port conforms with the IEEE standard 1149.1.
This standard defines a test access port and boundary-scan architecture for digital integrated
circuits.
The facilities defined by the standard seek to provide a solution to the problem of testing
assembled printed circuit boards and other products based on highly complex digital
integrated circuits and high-density surface-mounting assembly techniques. They also
provide a means of accessing and controlling design-for-test features build into digital
integrated circuits themselves.
PIN DESCRIPTION
TCK,TMS,TDI,TRST,TDO are used in this test operation.
•Test Clock Input (TCK)
TCK provides the clock for the test logic defined by this standard. Stored-state devices
contained in the test logic retain their state indefinitely when the signal applied to TCK is
stopped at 0.
•Test Mode Select Input (TMS)
The signal received at TMS is decoded by the TAP controlled to control test operation.
The signal presented at TMS is sampled by the test logic on the rising edge of TCK.
•Test Data Input (TDI)
Serial test instructions and data are received by the test logic at TDI.
The signal presented at TDI is sampled by the test logic on the rising edge of TCK.
•Test Reset Input (TRST)
The TRST input provides for asynchronous initialization of the TAP controller.
If TRST is included in the TAP, then the TAPcontroller is asynchronously reset to the Test-
Logic-Reset controller state when a logic 0 is applied to TRST.
•Test Data Input (TDO)
TDO is a serial output for test instructions and data from the test logic defined in this
standard.
Changes in the state of the signal driven through TDO occur only on the falling edge of
TCK. The TDO driver is set to its inactive drive state except when the scanning of data is in
progress.
C 1998 MITSUBISHI ELECTRIC CORPORATION
(11/15)
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M66244FP.PDF ] | |
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