PDF M66238FP Data sheet ( Hoja de datos )

Número de pieza	M66238FP
Descripción	STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
Fabricantes	Mitsubishi
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No Preview Available ! MITMSITUSBUISBHISI H〈DI I〈GDIITGAITLAALSASSPS〉 P〉 M662M36682F38PFP STASNTADNADRADRCDLOCLCOKCGKEGNEENREATROATROWRITWHITPHLLPLFLRFERQEUQEUNECNYCSYYSNYTNHTEHSEIZSEIRZER DESCRIPTION The M66238 is a LSI that incorporates a PLL synthesizer and a sync clock generator in it. The PLL synthesizer covers the range of 25MHz to 50MHz at the minimum steps of 3kHz. The sync circuit outputs a clock and a one-shot pulse which are synchronized with an external trigger signal. Setting a dividing ratio allows acquisition of sync clock outputs within the range of 0.78MHz to 25MHz. FEATURES • Sync clock output frequency range: 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 of 25 to 50MHz • Sync accuracy (jitter): ±3ns • Trigger input: Polarity selectable • One-shot pulse output: Polarity and width selectable • 5V power supply APPLICATION Pixel clock generator PIN CONFIGURATION (TOP VIEW) DIGITAL GND PIN DGND 1 RESET INPUT RESET → 2 CHIP SELECT INPUT CS → 3 SERIAL DATA INPUT SIN → 4 SERIAL CLOCK INPUT SCLK → 5 CLOCK OUTPUT XOUT ← 6 CLOCK INPUT XIN → 7 DIGITAL GND PIN DGND 8 DIGITAL POWER SUPPLY PIN DVCC 9  TCKI → 10 TEST PIN  TCKO ← 11 PLL OUTPUT CKO/PLLO ← 12 CLOCK OUTPUT CKOB ← 13 ONE-SHOT PULSE OUTPUT PULSE ← 14 SYNC OUTPUT POWER SUPPLY PIN VCCO 15 SYNC OUTPUT GND PIN GNDO 16 32 AGND ANALOG GND PIN 31 AVCC ANALOG POWER SUPPLY PIN 30 AGND ANALOG GND PIN 29 → RV VCO LOAD OUTPUT 28 AVCC ANALOG POWER SUPPLY PIN 27 AGND ANALOG GND PIN 26 ← CPIN FILTER CONNECT PIN 25 AGND ANALOG GND PIN 24 → CPOUT FILTER CONNECT PIN 23 DGND DIGITAL GND PIN 22 DVCC DIGITAL POWER SUPPLY PIN 21 → UP   TEST PIN 20 → DOWN  19 DVCC DIGITAL POWER SUPPLY PIN 18 DGND DIGITAL GND PIN 17 ← TR TRIGGER INPUT Outline 32P2W-A BLOCK DIAGRAM CHIP SELECT INPUT CS 3 SERIAL DATA INPUT SIN 4 SERIAL CLOCK INPUT SCLK 5 CLOCK INPUT XIN 7 CLOCK OUTPUT XOUT 6 RESET INPUT RESET 2 TRIGGER INPUT TR 17 SERIAL WRITE CONTROL CIRCUIT CRYSTAL OSCILLATOR CIRCUIT fin 12-BIT DIVIDER COMMAND REGISTER COMMAND CONTROL CIRCUIT 15 12 15-BIT COUNTER PHASE COMPARATOR VCO fvco 25MHz ~ 50MHz CHARGE PUMP 10 TCKI 11 TCKO TEST PIN SYNC/DIVIDER CIRCUIT ( )SYNC CLOCK GENERATOR 12 CKO/PLLO PLL OUTPUT 13 CKOB CLOCK OUTPUT 14 PULSE ONE-SHOT PULSE OUTPUT 21 20 24 UP DOWN CPOUT 26 CPIN 29 RV TEST PIN FILTER CONNECT PIN FILTER CONNECT PIN VCO LOAD OUTPUT 1 1 page MITSUBISHI 〈DIGITAL ASSP〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER 3. Dummy trigger generating command The internal status of sync clock generator becomes un- stable and a stable sync clock output (CKO) is not obtained after the power is turned on, after a reset is cleared or after an internal VCO oscillator frequency is set. To obtain a stable sync clock output, enter a trigger signal from the TR input af- ter VCO oscillator becomes stable, or enter a dummy trigger generating command from the MCU. The PLL synthesizer oscillator frequency after the cancellation of a reset depends on a default (See the register configuration). Set the command for address (A1, A0) = (1, 1). Data bit D0 D1 Description 0 The command must be stored two times continuously when a dummy trigger is generated. For the first time, set the dummy trigger generating command with D0=1. For the second time, set the dummy trigger generating command with D0=0. 1 The second setting becomes a sync edge and a clock begins to be output from CKO. After the first setting, CKO is in the halt state. 0 1 Default 0 0 In normal use: “0” D29 0 1 0 5 5 Page APPLICATION CIRCUIT EXAMPLE MITSUBISHI 〈DIGITAL ASSP〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER Digital power supply Programmable Interface 1MΩ 30pF Crystal oscillator 30pF 1 2 3 4 5 6 7 8 9 10 NC 11 12 13 14 15 16 Digital GND 32 31 30 29 28 27 26 25 24 23 22 21 NC 20 NC 19 18 17 Analog power supply 7.5kΩ Analog GND 2kΩ Programmable Interface 1.2kΩ 0.015µF 11 11 Page

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