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PDF M66236 Data sheet ( Hoja de datos )
| Número de pieza | M66236 | |
| Descripción | STANDARD CLOCK GENERATOR | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITMSUITBSIUSBHIS〈HDIG〈DITIAGLITALSSAPS〉SP〉
M662M36662F3P6FP
DESCRIPTION
M66236 is produced using the silicon gate CMOS process. It
is able to output clock input signal in sync with optional exter-
nal trigger input signal.
It features excellent synchronizing precision (jitter) over a
wide frequency band range.
FEATURES
• 5V single power supply (5V ±5%)
• Frequency band: 12 ~ 25MHz
• Synchronizing precision (jitter): ±5ns
• Output types
(1) Output of the same frequency as input clock, and its in-
version
(2) 1/2 divider clock output and its inversion
(3) One-shot pulse output
(4) Continuous clock output
• Noise in the positive direction to trigger input is removed by
built-in noise killer circuit
APPLICATION
Clock phase control for horizontal synchronization
STASNTDAANRDDACRLDOCCLKOGCEKNGEERNAETROARTOR
PIN CONFIGURATION (TOP VIEW)
CLOCK INPUT CLK IN → 1
TEST INPUT TEST1 → 2
TEST OUTPUT TEST2 ←
←ONE-SHOT PULSE
OUTPUT
PULSE
GND
←1/2 DIVIDER SYNC CLOCK
INVERTED OUTPUT CKO/2
←1/2 DIVIDER SYNC
CLOCK OUTPUT
CKO/2
GND
3
4
5
6
7
8
16 VCC
15 →TEST3 TEST OUTPUT
14 GND
13 ←TR TRIGGER INPUT
12 VCC
11 →CKO SYNC CLOCK OUTPUT
10 →CKO
SYNC CLOCK
INVERTED OUTPUT
9
→CNTCK
CONTINUOUS
CLOCK OUTPUT
Outline 16P2N-A
Note: Keep test pins (TEST 1 to 3) open.
BLOCK DIAGRAM
VCC
12
VCC
16
SYNC CLOCK SELECTOR CIRCUIT
CLOCK
INPUT
CLK IN 1
DELAY CLOCK
GENERATION CIRCUIT
11 CKO
SYNC CLOCK
OUTPUT
10 CKO
SYNC CLOCK
INVERTED OUTPUT
7
CKO/2
1/2 DIVIDER SYNC
CLOCK OUTPUT
6
CKO/2
1/2 DIVIDER SYNC
CLOCK INVERTED OUTPUT
9
CNTCK
CONTINUOUS
CLOCK OUTPUT
4
PULSE
ONE-SHOT
PULSE OUTPUT
TRIGGER
INPUT
TR
13
TEST
INPUT
TEST1 2
PHASE DETECTION CIRCUIT
5 8 14
GND GND GND
3 TEST2 TEST OUTPUT
15 TEST3 TEST OUTPUT
1
1 page  
MITSUBISHI 〈DIGITAL ASSP〉
M66236FP
STANDARD CLOCK GENERATOR
SWITCHING CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ±5%, GND = 0V)
Symbol
Parameter
Test conditions
∆t
tss(CKO)
tss(CKO)
tss(CKO/2)
tss(CKO/2)
tss(PULSE)
tss(CNTCK)
tsp(CKO)
tsp(CKO)
tsp(CKO/2)
tsp(CKO/2)
tw(PULSE)
tCH
tCL
fODUTY(CKO)
fODUTY(CKO)
Synchronizing precision (jitter)
Sync clock output start time
Sync clock inverted output start time
1/2 divider sync clock output start time
1/2 divider sync clock inverted output start time
One-shot pulse output start time
Continuous clock output start time
Sync clock output stop time
Sync clock inverted output stop time
1/2 divider sync clock output stop time
1/2 divider sync clock inverted output stop time
One-shot pulse output width
Sync clock-Input clock switching time
Input clock-Sync clock switching time
Sync clock output duty
Sync clock inverted output duty
CL=15pF
Limits
Min Typ
2tp – 10
30
Max
±5
tLp + 50
tLp + 50
tLp + 50
tLp + 50
40
40
2tp + 10
40
30
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
• tp = 1/fIN, tLp = tp × (100 – fDUTY)/100
• Switching test waveform
Input pulse level CLK IN: 0 to VCC
TR: 0 to 3V
Input pulse rise time: 3ns
Input pulse fall time : 3ns
Criterial voltage
Input voltage CLK IN: VCC/2
TR: 1.3V
Output voltage: VCC/2 for all outputs
• Capacitance: CL includes stray wiring capacitance and
probe input capacitance.
TEST CIRCUIT
INPUT VCC
PG DUT
50Ω
OUTPUT
CL
TIMING DIAGRAM
TR
CKO
CKO/2
CKO
CKO/2
PULSE
CNTCK
1.3V
tss
50%
tCL
50%
50%
3.0V
0V
VOH
VOL
VOH
VOL
TR
CKO
CKO/2
CKO
CKO/2
CNTCK
1.3V
tsp
50%
50%
tCH
3.0V
0V
VOH
VOL
VOH
VOL
TR 1.3V
tw(TR)
3.0V
1.3V
0V
PULSE
50%
tw(PULSE)
50%
VOH
VOL
5
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet M66236.PDF ] | |
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