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PDF M65761FP Data sheet ( Hoja de datos )
| Número de pieza | M65761FP | |
| Descripción | SPECIFICATION OF INTEGRATED CIRCUIT(QM-CODER) | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
SPECIFICATION OF INTEGRATED CIRCUIT
1. TYPE NO.
M65761FP
2. FUNCTION
2.1 CIRCUIT FUNCTION
2.2 BLOCK DIAGRAM
QM-Coder
see the third page
3. APPLICATION
FAX, PPC etc
4. OUTLINE
4.1 PACKAGE
4.2 OUTLINE DRAWING
100 Pin Plastic Molded Quad Flat Package (Fine Pitch)
[100P6S-A]
G465181
5. CIRCUIT DIAGRAM
DRAWING
6. PIN DIAGRAM
see the next page (2page)
7. OTHER SPECIFICATIONS see cover page of specification
1 page  
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
10. FUNCTIONAL DESCRIPTION OF PINS
Classification
Pin name
I/O BUF
Function
Host Bus I/F
RESET
CS
A0-3
BHE
WR
RD
D0-15
DMARQ
DMAAK
INTR
BUS16
I S H/W reset signal
I Chip select signal
I Internal register address select signal
I High-order(D8-15)access signal
I S Write strobe signal
I S Read strobe signal
IO 8 I/O data signal (D0-7 used on 8-bit bus)
O 2 Code data DMA request signal
I US Code data DMA acknowledge signal
O 2 Interrupt request signal
I U 8-bit bus (D0-7)and 16-bit bus(D0-15)function select bus.
Parallel
Image data
I/F
Serial
PD0-31
PDRQ
PDAK
PDRD
PDWR
PRDY
PTIM
PXCK
PXCKO
SVID
RVID
IO U2 Parallel image I/O bus (PD0-15 used on 16-bit bus)
O 2 Image data DMA request signal
I US Image data DMA acknowledge signal
I US Image data read strobe signal
I US Image data write strobe signal
O 2 Image data 1-line I/O start ready signal
I US Image data 1-line transfer section signal
I US Image data transfer clock signal
O 4 Image data transfer sync clock signal
I U Image data input signal
O 2 Image data output signal
Context I/F
CX0-11
PEUPE
SPIX
RPIX
XCLK
XWAIT
XRDY
XTIM
I
U Context input (CX0 can be fed back inside LSI)
(=PD0-11)
I U PE RAM update enable (learning function ON/OFF) (=PD15)
I U Coded image data input signal
(=SVID)
O 2 Decoded image data output signal
(=RVID)
O 4 Context data transfer clock signal
I US Context data transfer wait signal
O 2 Context data 1-stripe I/O start ready signal
(=PRDY)
I US Context data 1-stripe transfer section signal
(=PTIM)
Others
MCLK
TEST0-1
Vcc/GND
I Master clock input signal
I DS Test signal (should be connected to GND when normally used).
– – Power supply (+5V)/ground
Notes:Most of the context I/F signals are used in conjunction with the image data I/F signals.
∗ The input buffers of the input terminals (I and IO) are at TTL level.
Options are as follows.
(U:with pull-up resistors,D:with pull-down resistors,S:Schmitt trigger)
∗ Numbers (2,4,8) of the BUF column of the output terminals (O and IO) indicate current value. (one of 2,4,or 8mA)
5 Page 
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
(13) This register sets up various functions (W/R)
(address:D)
d7 d0
CONV_REG : TP LI OB HO HR VR HE VE
d0 (VE):Selects expansion in lengthwise direction during decoding. (0:Equal dimension, 1:∗2 expansion)
d1 (HE):Selects expansion sideways during decoding. (0:Equal dimension, 1:∗2 expansion)
∗d0 and d1 are possible only during decoding.
d2 (VR):Selects reduction in lengthwise direction during coding. (0:Equal dimension, 1:1/2 reduction)
d3 (HR):Selects sideways reduction during coding. (0:Equal dimension, 1:1/2 reduction)
∗d2 and d3 are possible only during coding.
d4 (HO):Selects thinning in sideways direction during coding. (0:simple thinning, 1:OR processing)
This reduction is valid only during coding.
Note 1:This lengthwise 1/2 reduction during coding is used for the simple thinning. (Odd lines are skipped)
Note 2: The number of lines for image data to be inputs when VR=1 for coding must be twice the value set by the register which
sets the number of lines.
Note 3:The number of lines for image data to be outputs when VE=1 for decoding must be twice the value set by the register which
sets the number of lines.
d5(OB):This selects if the leading 1 byte is discarded during decoding. (0:Normal processing (No discarding),
1:The leading 1 byte is discarded)
If a command to start processing the first the stripe decoding is issued during decoding while OB is set to "1", the leading 1 byte
of the input data is discarded. (Not used for decoding) If OB=0,the one of byte discarding process is not used. (Normal decoding
used) For example, this function is used by the Host 16 bits bus when the leading 1 byte of the input data word is an invalid data.
Note :Selecting this function is valid in case of the Host 8 bits bus and the external context mode also.
d6 (LI):Line memory initialization is prohibited. (0:Initialization specified, 1:Initialization prohibited)
When a command to start processing coding/decoding of the first stripe is issued, if L1=1, the initialization of the internal line
memory is prohibited. (The last image data of the immediately prior coding/decoding left in the line memory is used as the
leading reference line data o the next coding/ decoding.) When LI=0, the internal line memory is initialized. (All white (0) data is
used as the leading reference line data of the next coding /decoding.)In case when the previous stripe ended with SDNORM
during coding/decoding of multi-stripe by setting this bit in the initialization prohibit (1).
Note :Even when LI=1is set, this LI bit is cleared (0) and the internal line memory will be initialized the same line due to the fact that
the H/W reset is written into the external reset terminal or the system set up register.
d7 (TP):This selects the Typical prediction when coding and decoding. (0:Typical prediction off, 1:Typical prediction ON)
11. 3 Initialization of register
Each register is initialized as shown in the table below by writing H/W reset to the external RESET terminals or the system set up registers.
Table 11. 5 Initialization values for registers
Registers
Initialization values
System set up
Parameter set up
Command
Status
Interrupt enable
Number of pixels set up
Set up number of lines
Number of lines processed
Data buffer
Marker code set up
Marker code read out
Various functions set up
00h Notes
00h
00h
00h
00h
00h
00h
00h
Inderfinite
00h
00h
00h
Note:When writing H/W RESET into the System
Setup Register,the value written into is set
up in the System Setup Register.
11 Page | ||
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