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PDF M65669FP Data sheet ( Hoja de datos )
| Número de pieza | M65669FP | |
| Descripción | PICTURE-IN-PICTURE SIGNAL PROCESSING | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de M65669FP (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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PRELIMINARY
Notice ; This is not the final specification.
Some of information in this document are
subject to changes.
V3.1
MITSUBISHI DIGITAL TV ICs
M65669SP/FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
DESCRIPTION
APPLICATION
The M65669SP/FP is a PIP (Picture in Picture) signal
NTSC, PAL-M, PAL-N color TV
processing LSI, whose sub-picture input is composite
signal for NTSC, PAL-M, and PAL-N. The built-in field
RECOMMENDED OPERATING CONDITIONS
memory (144k-bit RAM) , V-chip data slicer and analog
circuitries lead the high quality PIP system low cost and
Supply voltage range ---------------------------------- 3.1 ~ 3.5 V
Operating frequency --------------------------------- 14.32 MHz
small size.
Operating temperature --------------------------------- -10 ~ 70 deg.
Input voltage (CMOS interface) "H" ----- VDD x 0.7 ~ VDD V
"L" ----- 0 ~ VDD x 0.3 V
FEATURES
Output current ( output buffer ) ------------------- 4 mA ( MAX )
Output load capacitance --------------------------- 20 pF ( MAX ) *1
* Built-in 144k-bit field memory ( sub-picture data storage)
Circuit current ---------------------------------------- - mA
* Internal V-chip data slicer (for sub-picture)
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS pins.
* Vertical filter for sub-picture ( Y signal )
*1 : Include pin capacitance ( 7 pF )
* Single sub-picture ( selectable picture size : 1/9 , 1/16 )
* Sub-picture processing specification ( 1/9 , 1/16 size) :
Quantization bits Y, B-Y, R-Y : 6 bits
Horizontal sampling 229 pixels ( Y ) , 57 pixels ( B-Y, R-Y )
Vertical lines 69/ 52 lines
* Frame ( sub-picture ) on/off
* Built-in analog circuits :
One 8-bit A/D converter ( for sub-picture signal)
Three 8-bit D/A converters ( for Y, U and V of sub-picture )
Sync-tip-clamp, VCXO ... etc..
Block diagram & Application examples
* IIC BUS control ( parallel/serial control) :
PIP on/off , Frame on/off ( programmable luma level),
Shown next pages
Sub-picture size ( 1/9, 1/16 ),
PIP position ( free position ), Picture freeze ,
Y delay adjustment, Chroma level, Tint, Black level,
Contrast ...etc..
PIN CONFIGURATION (TOP VIEW)
SWM 1
ACK 2
SDATA 3
SCLK 4
DVdd 5
DVss 6
BGPS 7
SCK 8
BGPM 9
FSC 10
TEST5 11
TEST6 12
SWMG 13
RESET 14
DVdd 15
DVss 16
MCK 17
CSYNCS 18
AVss(ad) 19
Vrb 20
Vrt 21
42 AVss(ana)
41 ADJ_Usub
40 Vdd(da)
39 YOUT
38 ADJ_Ysub
37 UOUT
36 ADJ_Vsub
35 VOUT
34 TESTEN
33 VD
32 HD
31 AVss(vcxo)
30 X'tal(P-N)
29 X'tal(P-M)
28 X'tal(NT)
27 BIAS
26 Filter
25 AVdd(vcxo)
24 AVdd(ad)
23 Vin(Sync sepa.)
22 Vin(ad)
Outline 42 Pin SDIP Package (M65669SP)
Outline 0.8mm pitch 42 Pin SOP Package (M65669FP)
( 1 / 15 )
1 page  
PRELIMINARY
Notice ; This is not the final specification.
Some of information in this document are
subject to changes.
V3.1
MITSUBISHI DIGITAL TV ICs
M65669SP/FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
PIN DESCRIPTION
Pin No. Name
I/O
Function
Remarks
1 SWM
CMOS output
PIP switch output
2 ACK
CMOS output
I2C SDA output (for high load SDA line use only)
3 SDATA
CMOS I/O (5V)*1 I2C SDA input/output
4 SCLK
CMOS input (5V)*1 I2C SCL input
5 DVdd1
6 DVss1
Digital Vdd
Digital Vss
Vdd for digital part
Vss for digital part
7 BGPS
CMOS output
Test output
8 SCK
CMOS input
Test input
connect to GND
9 BGPM
CMOS output
Test output
10 FSC
CMOS input
Test input
connect to GND
11 TEST5
CMOS input
Test input
connect to GND
12 TEST6
CMOS input
Test input
connect to GND
13 SWMG
CMOS input
connect to Vdd
14 RESET
CMOS input
Power on reset input
15 DVdd2
Digital Vdd
Vdd for digital part
16 DVss2
Digital Vss
Vss for digital part
17 MCK
CMOS input
Test input
connect to GND
18 CSYNCS
CMOS input
Sub picture external C-sync input
19 AVss (ADC) Analog Vss
Vss for internal ADC
20 VRB
Analog
Low level reference voltage output of ADC
21 VRT
Analog
High level reference voltage output of ADC
22 VIN (ADC)
Analog
Sub picture input of ADC
23 VIN (Sync Sep.) Analog
Sub picture input of sync sep. for sub picture
24 AVdd (ADC) Analog Vdd
Vdd for internal ADC
25 AVdd (VCXO) Analog Vdd
26 FILTER
Analog
Vdd for VCXO
VCXO filter voltage connection
27 BIAS
Analog
VXCO bias voltage connection
28 X'tal (NTSC) Analog
X'tal of NTSC connection
29 X'tal (PAL-M) Analog
X'tal of PAL-M connection
30 X'tal (PAL-N) Analog
X'tal of PAL-N connection
31 AVss (VCXO) Analog Vss
Vss for VCXO
32 HD
33 VD
34 TESTEN
CMOS input (5V)*1 Main picture HD input
CMOS input (5V)*1 MAIN picture VD input
CMOS input
Test input
connect to GND
35 VOUT
Analog
Sub picture V or B output
36 ADJ_Vsub
Analog
Referece voltage connection of DAC of V
37 UOUT
Analog
Sub picture U or G output
38 ADJ_Ysub
Analog
Referece voltage connection of DAC of Y
39 YOUT
Analog
Sub picture Y or R output
40 AVdd (DAC) Analog Vdd
41 ADJ_Usub
Analog
Vdd for DAC
Referece voltage connection of DAC of U
42 AVss (sub) Analog Vss
Vss for substrate
*1 ) (5V)means 5V I/F torelant
( 5 / 15 )
5 Page 
PRELIMINARY
Notice ; This is not the final specification.
Some of information in this document are
subject to changes.
V3.1
<The examples of serial byte transmission format>
MITSUBISHI DIGITAL TV ICs
M65669SP/FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
(1) The writing operation of the setting data (AAh) into M65669FP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
yes
S 24h A 00h A AAh A D E
no
is applied
on CLk for the
release of
output state
S : Operation of serial transmission start
A : Acknowledge detection
D : Dummy clock feed for the release of
acknowledge output state
E : Operation of serial transmission completion
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65669FP internal address of
04h ~ 06h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
no
yes
S 24h A 04h A FFh A 80h A EEh A D E
is applied
on CLk for the
release of
output state
(3) The reading operation of the setting data from M65669FP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
no
yes
S 24h A 00h A D E S 25h A $$h A'
is applied
on CLk for the
release of
output state
A' : Bus free operation by the
master (micro processor)
(11 / 15 )
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M65669FP.PDF ] | |
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