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PDF M65665 Data sheet ( Hoja de datos )

Número de pieza M65665
Descripción PICTURE-IN-PICTURE SIGNAL PROCESSING
Fabricantes Mitsubishi 
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No Preview Available ! M65665 Hoja de datos, Descripción, Manual

MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
APPLICATION
The M65665SP/FP is a PIP (Picture in Picture) signal
NTSC, PAL-M, PAL-N color TV
processing LSI, whose sub-picture input is composite
signal or component signals(Y /C or Y /U/V) f or NTSC, RECOMMENDED OPERATING CONDITIONS
PAL-M, and PAL-N. The built-in f ield memory (168k-bit
RAM) , V-chip data slicer and analog circuitries lead the
high quality PIP sy stem low cost and small size.
FEATURES
Supply v oltage range ------------------------ 3.2 ~ 3.5 V
Operating f requency ----------------------- 14.32 MHz
Operating temperature ------------------------ 0 ~ 70 deg.
Input v oltage (CMOS interf ace) "H" ----- VDD x 0.7 ~ VDD V
"L" ----- 0 ~ VDD x 0.3 V
Output current ( output buf f er ) ------------ 4 mA ( MAX )
Output load capacitance ---------------------- 20 pF ( MAX ) *1
Circuit current ----------------------------------- - mA
* Internal V-chip data slicer (f or sub-picture)
* Vertical f ilter f or sub-picture ( Y signal )
* Base band comb f ilter (2 Line)
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS pins.
*1 : Include pin capacitance ( 7 pF )
* Single sub-picture ( selectable picture size : 1/9 , 1/16 )
* Sub-picture processing specif ication ( 1/9 , 1/16 size) :
Quantization bits Y , B-Y, R-Y : 7 bits
Horizontal sampling 229 pixels (Y ), 57 pixels (B-Y , R-Y )
Vertical lines
69/ 52 lines
* Frame ( sub-picture ) on/of f
* Built-in analog circuits :
Two 8-bit A/D conv erter (f or sub-picture signal)
Three 8-bit D/A conv erters (f or Y , U and V of sub-picture)
Sy nc-tip-clamp, VCXO,OSD switch ... etc..
* IIC BUS control ( parallel/serial control) :
PIP on/of f , Frame on/of f ( programmable luma lev el),
Block diagram & Application examples
Shown next pages
Sub-picture size ( 1/9, 1/16 ),
PIP position ( f ree position ), Picture f reeze ,
Y delay adjustment, Chroma lev el, Tint, Black lev el,
Contrast
...etc..
PIN CONFIGURATION (TOP VIEW)
SWM
OSD_SEL
SDAT A
SCLK
DVdd
DVss
BGPS
SCK
BGPM
FSC
TEST5
TESTEN
SWMG
RESET
CSYNCS
AVdd(ad)
Vin(ad)
Uin(ad)
Vrb
Yin(ad)
Vrt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 Y(R)OUT
41 OSD_RIN
40 AGndDA
39 U(G)OUT
38 OSD_GIN
37 VZ
36 V(B)OUT
35 OSD_BIN
34 VddDA
33 VD
32 HD
31 AVss(vcxo)
30 X'tal(P-N)
29 X'tal(P-M)
28 X'tal(NT )
27 BIAS
26 Filter
25 AVdd(vcxo)
24 CVBSin(ad)
23 AVss(ad)
22 Cin(ad)
Outline 42 Pin SDIP Package (M65665SP)
Outline 0.8mm pitch 42 Pin SOP Package (M65665FP)
MITSUBISHI
ELECTRIC
1

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M65665 pdf
MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
PIN DESCRIPTION
Pin No. Name
1 SWM
2 OSD_SEL
3 SDATA
4 SCLK
5 DVdd1
6 DVss1
7 BGPS
8 SCK
9 BGPM
10 FSC
11 TEST5
12 TESTEN
13 SWMG
14 RESET
15 CSYNCS
16 AVdd (ADC)
17 VIN (ADC)
18 UIN (ADC)
19 VRB
20 Y IN (ADC)
21 VRT
22 CIN
23 AVss (ADC)
24 CVBSIN
25 AVdd (VCXO)
26 FILTER
27 BIAS
28 X'tal (NTSC)
29 X'tal (PAL-M)
30 X'tal (PAL-N)
31 AVss (VCXO)
32 HD
33 VD
34 AVdd (DAC)
35 OSDBIN
36 VOUT
37 VZ
38 OSDGIN
39 UOUT
40 AVss (sub)
41 OSDRIN
42 YOUT
I/O Function
CMOS output
CMOS input
PIP switch output
Output OSD select
CMOS I/O(5V)*1 I2C SDA input/output
CMOS input(5V)*1 I2C SCL input
Digital Vdd
Vdd f or digital part
Digital Vss
CMOS output
CMOS input
CMOS output
Vss f or digital part
Test output
Test input
Test output
CMOS input
CMOS input
CMOS input
Test input
Test input
Test input
CMOS input
CMOS input
Power on reset input
CMOS input
Analog Vdd
Analog
Analog
Analog
Analog
Sub picture external C-sy nc input
Vdd f or internal ADC
Sub picture V input of ADC
Sub picture U input of ADC
Low lev el ref erence v oltage output of ADC
Sub picture Y input of ADC
Analog
Analog
Analog Vss
High lev el ref erence v oltage output of ADC
Sub picture C input of ADC
Vss f or internal ADC
Analog
Sub picture CVBS input of ADC
Analog Vdd
Analog
Vdd f or VCXO
VCXO f ilter v oltage connection
Analog
Analog
VXCO bias v oltage connection
X'tal of N TSC connection
Analog
Analog
X'tal of PAL-M connection
X'tal of PAL-N connection
Analog Vss
Vss f or VCXO
CMOS input(5V)*1 Main picture HD input
CMOS input(5V)*1 MAIN picture VD input
Analog Vdd
Vdd f or DAC
Analog
Analog
OSD input of B
Sub picture V or B output
Analog
Analog
Voltage ref erence output of D AC
OSD input of G
Analog
Analog Vss
Analog
Analog
Sub picture U or G output
Vss f or DAC
OSD input of R
Sub picture Y or R output
Remarks
connect to GND
connect to GND
connect to GND
connect to GND
connect to Vdd
*1 ) (5V)means 5V I/F torelant
MITSUBISHI
ELECTRIC
5

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M65665 arduino
MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
<The examples of serial byte transmission format>
(1) The writing operation of the setting data (AAh) into M65665FP internal address of 00h
T ransm i ssi o n
Activation
Confirmation
of bus free
(DATA='H')
yes
S 24h A 00h A AAh A D E
no
is applied
on CLk for the
release of
output state
S : Operation of serial transmission start
A : Acknowledge detection
D : Dummy clock feed for the release of
acknowledge output state
E : Operation of serial transmission completion
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65665FP internal address
of 04h ~ 06h
T ransm i ssi o n
Activation
Confirmation
of bus free
(DATA='H')
no
yes
S 24h A 04h A FFh A 80h A EEh A D E
is applied
on CLk for the
release of
output state
(3) The reading operation of the setting data from M65665FP internal address of 00h
T ransm i ssi o n
Activation
Confirmation
of bus free
(DATA='H')
no
yes
S 24h A 00h A D E S 25h A $$h A'
is applied
on CLk for the
release of
output state
A' : Bus free operation by the
master (micro processor)
MITSUBISHI
ELECTRIC
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