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PDF M64897GP Data sheet ( Hoja de datos )
| Número de pieza | M64897GP | |
| Descripción | PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC
DESCRIPTION
The M64897GP is a semiconductor integrated circuit consisting of
PLL frequency synthesizer for TV/VCR/PC using I2C BUS control.
It contains the prescaler with operating up to1.3GHz, 4 band drivers
and DC-DC converter for Tuning voltage.
FEATURES
• Built-in DC-DC converter for Tuning voltage
• 4 integrated PNP band drivers
(Io=30mA, Vsat=0.2V typ@Vcc1 to 10V)
• Built-in prescaler with input amplifier (f max=1.3GHz)
• PLL lock/unlock status display out put
(Built-in pull up resistor)
• X’tal 4MHz is used to realize 3 type of tuning steps
(Divider ratio 1/512, 1/640, 1/1024)
• Software compatible with M64894
• Built-in Power on reset system
• Small Package (SSOP)
APPLICATION
PC, TV, VCR tuners
PIN CONFIGURATION (TOP VIEW)
PRESCALER
INPUT
GND
SUPPLY
VOLTAGE 1
SUPPLY
VOLTAGE 2
fin
GND
VCC1
VCC2
BS4
1
2
3
4
5
BAND
SWITCHING
OUTPUTS
BS3 6
BS2 7
BS1
DC-DCSUPPLY
VOLTAGE
VDC
PEACK CURRENT
DETECT
Ipk
8
9
10
20 Xin
19 ADS
18 SDA
CRYSTAL
OSCILLATOR
CHIP ADDRESS
INPUT
DATA INPUT
17 SCL CLOCK INPUT
16
LD/ftest
LD/ftest
OUTPUT
15 ADC A/D INPUT
14 Vin
13 Vtu
12 +B
11 SWE
FILTER INPUT
TUNING
OUTPUT
SUPPLY
VOLTAGE
SWITCHING
OUTPUT
Outline 20P2E-A
RECOMMENDED OPERATING CONDITION
Supply voltage range..............................................VCC1=4.5 to 5.5V
VCC2=VCC1 to 10V
Rated supply voltage...........................................................VCC1=5V
VCC2=VCC1
BLOCK DIAGRAM
VCC1
3
Xin 20
OSC
f REF DIVIDER
fin 1
AMP
1/8
SELECTER
LATCH
2
LATCH
15
DIV.
VDC
9
SQ
R
-
+ Vreg
SCL 17
SDA 18
ADS 19
1/32,1/33
15bit
PROGRAMMABLE DIVIDER
PHASE
DETECTOR
CHARGE
PUMP
BUS CONTROLLER
ADDRESS SELECT
1 LOCK
DETECTOR
5
CP TEST
LATCH
BAIS / BAND SWITCH DRIVER
4
1
3
5-LEVEL A/D
Power
On Reset
4567
8
VCC2
BS4
BS3
BS2
BS1
2
GND
15
ADC
Ipk
10
11 SWE
12 +B
13 Vtu
OS
14 Vin
16 LD/ftest
1
1 page  
MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC
METHOD OF SETTING DATA
The input information to consit of 2 or data of 4bytes to lead to Chip
Address is received in I2C bus receiver. It shows a definition of bus
protocol admitted in the following.
1_STA CA CB BB STO
2_STA CA D1 D2 STO
3_STA CA CB BB D1 D2 STO
4_STA CA D1 D2 CB BB STO
STA : Start condition
STO : Stop condition
CA : Chip address
CB : Control data byte
BB : BandS.W. data byte
D1 : Divider data byte
D2 : Divider data byte
The information of 5 bytes necessary for circuit operation is chip
address and control data, bandS.W. data of 2 bytes and divider byte
of 2 bytes. After the chip address input, 2 or data of 4 bytes are
received. Function bit is contained the first and the third data byte to
distinguish between divider data and control data, band data, and
"0" goes ahead of divider data, and "1" goes ahead of control data,
bandS.W. data.
SDA
SCL
S
STA
1-7 8
ADDRESS
CA
R/W
9
ACK
1-7 8
DATA
9
ACK
1-7 8
DATA
9
ACK
P
STO
Write mode format
Address Byte
Devider Byte1
Devider Byte2
Control Byte1
Band SW Byte
Byte
Read mode format
Address Byte
Status Byte1
Byte
MSB
LSB
1 1 0 0 0 MA1 MA0 0 A
0
N14 N13 N12 N11 N10
N9
N8
A
N7 N6 N5 N4 N3 N2 N1 N0
A
1 X T2 T1 T0 Rsa Rsb OS A
X X X X BS4 BS3 BS2 BS1 A
MSB
LSB
1 1 0 0 0 MA1 MA0 1 A
POR FL
X
X
X A2 A1 A0 A
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet M64897GP.PDF ] | |
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