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PDF M64811AGP Data sheet ( Hoja de datos )

Número de pieza M64811AGP
Descripción 1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
Fabricantes Mitsubishi 
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MITSUBISHI ICs (COMMUNICATION)
M64811AGP
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M64811AGP is a 1.1GHz/500MHz band two-system
one-chip PLL frequency synthesizer .
Using a high performance Bi-CMOS process , the product
contains one two-modulus (1/32 and 1/33) prescaler that
accepts inputs up to 1.1GHz and another two-modulus
(1/16 and 1/17) prescaler that accepts inputs up to
500MHz ,thus helping make the equipment compact .
FIN1
GND
CPS
SI
LE
1
2
3
4
5
16 PD1
15 Vcc
14 XIN
13 XOUT
12 XBo
FEATURES
SLEEP1
SLEEP2
6
7
11 LOCK
10 GND
• Operating supply voltage : 2.7V~3.6V
• Operating temperature : -30°C~+85°C
FIN2 8
9 PD2
• 2 PLL systems (1.1GHz and 500MHz) are on one chip .
PLL1 : 700MHz~1.1GHz PLL2 : 100MHz~500MHz
• Low power consumption (Icc=8mA Typ at Vcc=3V) .
• Dividing ratio setting ranges :
FIN1 for 1.1GHz VCO• • • • • N(VCO1)=1,024~131,071
FIN2 for 500MHz VCO• • • • • N(VCO2)=256~131,071
OSC for Fref • • • • • • • • • • • • • N(Fref)=5~2,047
• Each loop has input pin for sleep mode .
Power supplies to 2 loops can be independently turned ON/OFF .
Also can be controlled by the serial data . (When SLEEP1 and SLEEP2 is "H" . )
• The PLL standard oscillation circuit can adopt a B-E Colpitts type oscillation circuit to from a stable
oscillation circuit.
• Current controlled charge pump . (Icp=±2mA const.)
• Locked condition detecting output
If a phase difference smaller than 3 times (t) of the OSC period continues for 15 periods or
longer , the condition is judged as locked, and the LOCK terminal goes to "L" .
(When , for example , fosc=19.2 MHz , t=156 ns)
• PLL lock/unlock status indicate function .
(Judged in the system turned on if the other system is turned off . )
• Small package (16pin SSOP, lead pitch : 0.65mm)
APPLICATION
• Digital cordless phone (CT2)
• Digital cellular phone (PDC)
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M64811AGP pdf
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
Note 4) Power on/off control of PLL system is set by DA , DB , and DF .
External Control Pin
Serial Data
SLEEP1 SLEEP2 DA
DB DC
L L*
**
L H0 0 *
L H0 1 *
L H1 0 *
L H1
H L0
1*
0*
H L0
H L1
1*
0*
H L1
1*
H H1
11
H H1
H H1
10
01
H H1
00
H H0
11
H H0
10
H H0
01
H H0
00
ON;Power on , OFF;Power off
PLL1
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
Description
PLL2
OSC
OFF
ON
ON ON
OFF
ON
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
ON
OFF
OFF
OFF
ON
ON ON
ON ON
OFF
ON
OFF
ON
ON ON
ON ON
XBo
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
Note 5) DD and DE are used to select latched data to be updated.
Data
DD DE
00
Unused.
Description
0 1 Data latched for local oscillator 1 is updated.
1 0 Data latched for local oscillator 2 is updated.
1 1 Data latched for reference frequency .
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