|
|
PDF M64285K Data sheet ( Hoja de datos )
| Número de pieza | M64285K | |
| Descripción | CMOS Image Sensor(Image inputting systems for gaming devices / interface systems / security / surveillance /) | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M64285K (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
|
No Preview Available !
Technical Data Sheet
MITSUBISHI
PRELIMINARY
MITSUBISHI CMOS Image Sensor
M64285K
1. General Description
M64285K is a 32x32 pixel CMOS image sensor with the built-in image processor and the
analog conditioning function. It contains the information compressing and parallel
processing functions. It makes it possible to realize the image information input system to
become highly functional, smaller in size, faster in speed, and lower in power consumption.
2. Features
* Single 5.0V power supply.
* Low power dissipation (Typ. 15mW)
* Projection processing of two dimensional (2D) image to one dimensional (1D) image.
(Column and Row Projection)
* Outputting the average data of the overall image area
* Adjusting the gain, black level, and the data offset
* Variable data rate : 4φ ~ 64φ / pixel ( φ is the clock cycle time )
* It is possible to use 8 bit microcontroller for controlling purposes.
3. Application
Image inputting systems for gaming devices, interface systems, security, surveillance,
factory automation, etc.
( 1 / 26 )
Specifications and information herein are subject to change without notice.
02 / 05 / 01
Ver. 1.1E_01
1 page  
Technical Data Sheet
MITSUBISHI
PRELIMINARY
MITSUBISHI CMOS Image Sensor
M64285K
10. Electrical Characteristics (AC)
( Ta = 25 °C )
Symbols
Items
Min.
Typ.
Max.
Units
t c (CLK)
CLK cycle time *
0.5 0.5 2 µs
t WH (CLK)
CLK pulse width ( "H" level )
240
-
- ns
t WL (CLK)
CLK pulse width ( "L" level )
240
-
- ns
t r (CLK)
CLK rise time
- - 10 ns
t f (CLK)
CLK fall time
- - 10 ns
t c (SCLK)
SCLK cycle time
0.5 -
- µs
t WH (SCLK)
SCLK pulse width ( "H" level )
240
-
- ns
t WL (SCLK)
SCLK pulse width ( "L" level )
240
-
- ns
t r (SCLK)
SCLK rise time
- - 10 ns
t f (SCLK)
SCLK fall time
- - 10 ns
t WL (RESET)
RESET pulse width ( "L" level )
200
-
- ns
t D (RESET-SIN)
RESET-SIN delay time
100 -
- ns
t S (SIN)
SIN setup time
50 -
- ns
t H (SIN)
SIN hold time
50 -
- ns
t D (SIN-LOAD)
SIN-LOAD delay time
( Note 1 )
-
- ns
t D (LOAD-SIN)
LOAD-SIN delay time
( Note 2 )
-
- ns
t S (LOAD)
LOAD setup time
50 -
- ns
t H (LOAD)
LOAD hold time
50 -
- ns
t S (START)
START setup time
50 -
- ns
t H (START)
START hold time
50 -
- ns
t DR (CLK_STRB) CLK-STRB delay time (Rise) **
-
- 100 ns
t DF (CLK_STRB) CLK-STRB delay time (Fall) **
-
- 100 ns
t r (VOUT)
VOUT stabilization time **
-
600
-
ns
t H (VOUT)
VOUT hold time
-
-
( Note 3 )
µs
* Hereafter CLK cycle time is written to be φ.
** Load Capacitance = 50 pF
t t tNote 1: D (SIN-LOAD) ≥ 100 + -S (SIN) S (LOAD)
t t tNote 2: D (LOAD-SIN) ≥ 100 + -S (LOAD) S (SIN)
Note 3: t H (VOUT) ≤ ( DOC - φ / 2 ) x t C (CLK) - 0.1 [µs]
DOC: see the explanation of DR register.
( 5 / 26 )
Specifications and information herein are subject to change without notice.
02 / 05 / 01
Ver. 1.1E_01
5 Page 
Technical Data Sheet
MITSUBISHI
PRELIMINARY
MITSUBISHI CMOS Image Sensor
M64285K
11.4. Data Rate Setting Register, DR (4 bits)
M64285K is capable of varying the data output cycles, DOC ( = 1 / [data rate] ), in 16 steps
to meet various speeds of the A/D converters. DOC is set by the DR register. Please note
that DOC affects the accumulation time setting.
Register Range
0000 B ~ 1111B
Data Output Cycles : DOC
4 φ ~ 64 φ
Step
4φ
Number of Steps
16
* The Register value of 4 figures is the arrangement of DR3, DR2, DR1, DR0 in this order.
* DOC = ( [Register Value] + 1 ) x [Step]
* The setting of the accumulation time varies depending on DOC, since the status of the internal
counter depends on the varied data rates.
ex ) System Clock
2.0 MHz
1.23 MHz
1.0 MHz
0.5 MHz
Data Output Cycle Time
2.0 ~ 32.0 µs
3.3 ~ 52.0 µs
4.0 ~ 64.0 µs
8.0 ~ 128.0 µs
Data Rate
500 ~ 31.2 kHz
307.5 ~ 19.2 kHz
250 ~ 15.6 kHz
125 ~ 7.8 kHz
11.5. Accumulation Time Setting Register, C (16 bits)
The accumulation time of 2D image is set based on the time step needed to read out one
line. In the Projection image continuous output modes or in snapshot modes, the time step is
32φ, however, there are lower limits of the setting time in projection image continuous
output modes decided by the readout time.
Although it is possible to set a very long accumulation time on the register in the order of
second, it does not necessarily mean the analog function is guaranteed.
11.5.1. 2D Image : Continuous Output
* MD = 0000
* [Accum. Time] = [Register Value] x [Step]
Register Range
0000 H ~ FFFF H
Min.
0φ
Step [ φ ]
38 + DOC x 32
Number of Steps
65, 536
ex ) DOC
System Clock Range of Accum. Time
Step
4 φ 2.0 MHz
0.5 MHz
64 φ 2.0 MHz
0.5 MHz
0 ~ 5.4 s
0 ~ 21.8 s
0 ~ 68.4 s
0 ~ 273.4 s
83 µs
332 µs
1043 µs
4172 µs
* The output time [φ] for 1 frame is
( 38 + DOC x 32 ) x 33
( 38 + DOC x 32 ) x ( [Register Value] + 2 )
( [C Register Value ≤ 001E H )
( [C Register Value] ≥ 001F H )
( 11 / 26 )
Specifications and information herein are subject to change without notice.
02 / 05 / 01
Ver. 1.1E_01
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet M64285K.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M64285FP | CMOS Image Sensor(Image inputting systems for gaming devices / Toys / PC interface systems) | Mitsubishi |
| M64285K | CMOS Image Sensor(Image inputting systems for gaming devices / interface systems / security / surveillance /) | Mitsubishi |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |