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PDF M62398FP Data sheet ( Hoja de datos )
| Número de pieza | M62398FP | |
| Descripción | 8BIT 12CH I2C BUS D.A CONVERTER WITH BUFFER AMPLIFIERS | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI <Dig./Ana. INTERFACE>
M62398P,FP
8BIT 12CH I2C BUS D–A CONVERTER WITH BUFFER AMPLIFIERS
GENERAL DESCRIPTION
The M62398P,FP is a 12V type CMOS 12-channel D–A
converters with output buffer amplifiers.
It can communicate with a microcontroller via few wiring
thanks to the adoption of the two-line I2C BUS.
The output buffer amplifier employs AB class output with
sinking and sourcing capability of more than 2.5mA ,and an
output voltage range is nearly between ground and VrefU.
Maximum 8 ICs can be connected to a bus by using three
chip-set pins , so that it is possible to handle up to 96
channels.
FEATURES
• I2C BUS serial data method
• Wide output range
Nearly between ground and VrefU(0~12V).
• High output current drive capability
Over ±2.5mA
• 2 setting voltage ranges by dual input pins for upper
voltage references (VrefU1,U2)
PIN CONFIGURATION (TOP VIEW)
R1
SCL 2
SDA 3
Ao7 4
Ao8 5
Ao9 6
Ao10 7
Ao11 8
Ao12 9
VrefL 10
VrefU1 11
GND 12
24 CS0
23 CS1
22 CS2
21 VDD
20 VCC
19 Ao6
18 Ao5
17 Ao4
16 Ao3
15 Ao2
14 Ao1
13 VrefU2
Outline 24P4D (P)
24P2N-B (FP)
APPLICATION
Conversion from digital control data to analog control data for both consumer and industrial equipment.
Gain control and automatic adjustment of DISPLAY-MONITOR or CTV.
BLOCK DIAGRAM
CS0 CS1 CS2
24 23 22
VDD Vcc Ao6
21 20 19
Ao5
18
Ao4
17
Ao3
16
Ao2
15
Ao1
14
VrefU2 GND
13 12
CHIP SELECT
R2 R2 R2 R2 R2 R2
R1 R1 R1 R1 R1 R1
8bit upper
8bit upper
8bit upper
8bit upper
8bit upper
8bit upper
segment R-2R segment R-2R segment R-2R segment R-2R segment R-2R segment R-2R
8bit Latch
8bit Latch
8bit Latch
8bit Latch
8bit Latch
8bit Latch
8
8bit Latch
8bit Latch
8bit Latch
8bit Latch
8bit Latch
8bit Latch
8bit upper
8bit upper
8bit upper
8bit upper
8bit upper
8bit upper
segment R-2R segment R-2R segment R-2R segment R-2R segment R-2R segment R-2R
R2 =2.4
R1
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
1
23
4
R SCL SDA Ao7
5
Ao8
6
Ao9
7
Ao10
8
Ao11
9
Ao12
10 11
VrefL VrefU1
MITSUBISHI ELECTRIC
1997-5-28D.rev (1 / 7)
1 page  
MITSUBISHI <Dig./Ana. INTERFACE>
M62398P,FP
8BIT 12CH I2C BUS D–A CONVERTER WITH BUFFER AMPLIFIERS
I 2C- BUS FORMAT
STA SLAVE ADDRESS W A SUB ADDRESS A DAC DATA A STP
DIGITAL DATA FORMAT
•SLAVE ADDRESS
First
Last
1 0 0 1 A2 A1 A0
(SLAVE ADDRESS)
CHIP SELECT DATA
•DAC DATA
First
MSB
D7 D6 D5 D4 D3 D2 D1
Last
LSB
D0
•SUB ADDRESS
First
XXX
Last
X S3 S2 S1 S0
Don't care
CHANNEL SELECT DATA
(1)CHIP SELECT DATA
MSB
LSB
A2 A1 A0 CS2 CS1 CS0
000 000
001 001
010 010
111 111
Lower 3bits(A0,A1,A2) are a programmable
address. This IC is accessed only when the
lower 3 bits data of slave address coincide with
the data of CS0 to CS2.(refer to the upper table)
(2)CHANNEL SELECT DATA
MSB
LSB
S3 S2 S1 S0
Channel selection
00 00
Don't care.
00 01
00 10
ch1 selection
ch2 selection
10 11
11 00
11 01
ch11 selection
ch12 selection
Don't care.
11 11
Don't care.
(3)DAC DATA
First
MSB
Last
LSB
D7 D6 D5 D4 D3 D2 D1 D0
DAC output
0 0 0 0 0 0 0 0 (VrefU-VrefL)/256 x 1 x 2.4 + VrefL
0 0 0 0 0 0 0 1 (VrefU-VrefL)/256 x 2 x 2.4 + VrefL
0 0 0 0 0 0 1 0 (VrefU-VrefL)/256 x 3 x 2.4 + VrefL
0 0 0 0 0 0 1 1 (VrefU-VrefL)/256 x 4 x 2.4 + VrefL
1 1 1 1 1 1 1 0 (VrefU-VrefL)/256 x 255 x 2.4 + VrefL
1 1 1 1 1 1 1 1 (VrefU-VrefL) x 2.4 + VrefL
MITSUBISHI ELECTRIC
1997-5-28D.rev ( 5 / 7)
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet M62398FP.PDF ] | |
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