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PDF M62352AGP Data sheet ( Hoja de datos )

Número de pieza M62352AGP
Descripción 8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
Fabricantes Mitsubishi 
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MITSUBISHI <Standard Linear IC>
M62352AGP
8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION
M62352A is a CMOS structured semiconductor integrated ciruict integrating
12 channels of built-in D-A converters with high performance buffer operational
amplifierf or each channel output.
3-wire serial interface (DI,CLK,LD) method is used for the taransfer format
Pin configuration(Top View)
of digital data to allow connection with microcomputer with minimum wiring
Do terminal is provided to allow cascading serial use.
Built-in buffer operational amplifiers are designed to operate or full-swing in the
whole voltage range from Vcc to GND for each input/output. And their higher stability
for capacitive load perfectly fits in to the use for electronic volume (VCA)
or the replacement for semi-variable resistor for tuning.
FEATURES
12 bit serial data input (3 wire serial data transfer method, DI, CLK, LD)
VSS 1
AO3 2
AO4 3
AO5 4
AO6 5
AO7 6
AO8 7
AO9 8
AO10 9
VDD 10
20 GND
19 AO2
18 AO1
17 DI
16 CLK
15 LD
14 DO
13 AO12
12 AO11
11 VCC
Corresponds to TTL input for digital input (VINH 2V, VINL0.8V)
R-2R + segment method high performance 12 channel 8 bit D-A converters
12ch buffer operational amplifiers opperating in the whole voltage range from Vcc to
GND
Outline 20P2E-A
Buffer operational amplifiers with high oscillation stability for capacitive load
APPLICATION
Adjustment or control of industrial or home-use electronic
equipments such as VTR camera, VTR set, TV, and CRT display.
20 19 18 17
16 15 14 13 12
11
8bit R-2R
+segment
D-A converter
L
D0
10 11
D-A
(12)
ch3
8bit R-2R
+segment
D-A converter
4
5 6 7 8 9 10
( 1/ 6)
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M62352AGP pdf
MITSUBISHI <Standard Linear IC>
M62352AGP
8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
<AC characteristics> (VCC, VrefU=5V ± 10% , VCC ≥ VrefU, GND, VrefL=0.0V, Ta=-20 ~ +85ºCunless otherwise specified.)
Symbol
Parameter
Conditions
Ratings
MIN TYP MAX
Unit
tCKL
tCKH
tCR
tCF
tDCH
Clock "L" puise width
Clock "H" pulse width
Clock rise time
Clock fall time
Data setup time
200 ns
200 ns
200 ns
30 ns
tCHD
tCHL
tLDC
tLDH
tDO
tLDD
Data hold time
LD setup time
LD hold time
LD "H" hold time
Data output delay time
D-A output settling time
CL≤ 100pF
CL ≤ 100pF,VAO:0.5 4.5V
The time until the output becomes
the final value of 1/2 LSB
60
200
100
100
70
ns
ns
ns
ns
350 ns
300 s
Measurement circuit
input
DUT
output
C L 100pF
TIMING CHART
CLK
DI
LD
tCR tCKH tCF
tCKL
tDCH
tCHD
tCHL
AO1~ AO12
output
DO output
tDO
tCHL
tLDH
tLDC
tLDD
t DO
( 5 / 6)
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