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PDF M62320FP Data sheet ( Hoja de datos )

Número de pieza M62320FP
Descripción 8-BIT I/O EXPANDER for I2C BUS
Fabricantes Mitsubishi 
Logotipo Mitsubishi Logotipo



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No Preview Available ! M62320FP Hoja de datos, Descripción, Manual

GENERAL DESCRIPTION
The M62320P/FP is a CMOS 8-bit I/O expander which has
serial to parallel and parallel to serial data converting
functions.
It can communicate with a microcontroller via few wiring
thanks to the adoption of the two-line I2 C BUS.
Parallel data I/O terminal can be set to input or output
mode alternatively in individual bits.
Maximum 8 ICs can be connected to a bus by using three
chip-select pins, so that it is possible to handle up to 64 bits
data.
FEATURES
• Simple two-line (SCL and SDA) communication with a
microcontroller.
• 8-bit data conversion between serial and parallel by
I2C BUS.
• Built-in power-on reset.
APPLICATION
I/O port expansion for a microcontroller.
Data conversion between serial and parallel in
microcontroller peripherals.
BLOCK DIAGRAM
CS0 CS1 CS2
16 15 14
CHIP-SELECT
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
8-BIT I/O EXPANDER for I2 C BUS
PIN CONFIGURATION(TOP VIEW)
SO 1
SCL 2
SDA 3
D0 4
D1 5
D2 6
D3 7
GND 8
16 CS0
15 CS1
14 CS2
13 VDD
12 D7
11 D6
10 D5
9 D4
Outline 16P4(P)
16P2N(FP)
SCL 2
SDA 3
VDD 13 POWER-ON
GND 8 RESET
I2C BUS
TRANSCEIVER
SHIFT
REGISTER
Output Data
8
Input/Output
8
8
OUTPUT DATA
LATCH
I/O SETTING
DATA LATCH
INPUT DATA
LATCH
88
ÅI@/O PORT
8
Input Data
1 SO
12 11 10 9 7 6 5 4
D7 D6 D5 D4 D3 D2 D1 D0
MITSUBISHI ELECTRIC
2/20,1998(rev) ( 1 / 9 )

1 page




M62320FP pdf
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
8-BIT I/O EXPANDER for I2 C BUS
FUNCTIONAL BLOCKS
I2C BUS interface
The I2C BUS interface recognizes start/stop conditions, a slave address and a write/read mode selection
by receiving SDA,SCL,CS0,CS1 and CS2 signals and then the latch pulses, dedicated to each data latch
are generated.
Data Latch
This IC has 3 types of data latch : the I/O setting data latch, the input data latch and the output data latch
and each latch is controlled by the I2 C BUS interface.
• I/O setting data latch
These latches set input- or output-state of each parallel data terminals (D0 to D7). They are set at the next
byte after receiving the slave address byte in the write mode from the master. In case this latch is set to
high, the data is transferred from the I2 C BUS interface to the parallel data terminals. In the opposite
transmission : from the parallel data terminals to the I2 C BUS, it is set to low.
• Output data latch
In the write mode, the data from the I2 C BUS to the parallel data terminals is latched. When the master
transmits output data after a setting in write mode, the output data is taken into the latches.
• Input data latch
In the read mode, the data of parallel data terminals is latched in the input data latches. The input data is
taken into the latches from the parallel data terminals on every 8th negative edge of SCL clock . The
latched data is output to the master through the sift resistor. On the output terminal assigned by the I /
O setting latch, the input data latch takes the state of the output terminal.
Parallel input / output port
In case I/O setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance and
is able to accept a input. In another case I/O setting latch is set to high (output mode), each parallel
terminal outputs a data according to the state of the output data latch.
Power on reset
When power is turned on, each latch is reset and then the parallel data I/O terminals become
hi-impedance (input mode).
MITSUBISHI ELECTRIC
2/20,1998(rev) ( 5 / 9 )

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