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PDF M5M5V4R08J-15 Data sheet ( Hoja de datos )
| Número de pieza | M5M5V4R08J-15 | |
| Descripción | 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
MITSUBISHI LSIs
M5M5V4R08J-12,-15,-20
1997.02.06 Rev.D
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V4R08J is a family of 524288-word by 8-bit static PIN CONFIGURATION (TOP VIEW)
RAMs, fabricated with the high performance CMOS silicon
gate process and designed for high speed application.
The M5M5V4R08J is offered in a 36-pin plastic small outline
J-lead package(SOJ).
These device operate on a single 3.3V supply, and are directly
TTL compatible. They include a power down feature as well.
FEATURES
• Fast access time M5M5V4R08J-12 •••• 12ns(max)
M5M5V4R08J-15 •••• 15ns(max)
M5M5V4R08J-20 •••• 20ns(max)
• Low power dissipation Active •••••••••• 363mW(typ)
Stand by ••••••• 3.3mW(typ)
• Single +3.3V power supply
• Fully static operation : No clocks, No refresh
• Common data I/O
• Easy memory expansion by S
• Three-state outputs : OR-tie capability
• OE prevents data contention in the I/O bus
• Directly TTL compatible : All inputs and outputs
A0 1
address
inputs
chip select
input
data inputs/
outputs
A1
A2
A3
A4
S
DQ1
DQ2
2
3
4
5
6
7
8
(3.3V) VCC 9
(0V)
data
inputs/
GND
DQ3
10
11
outputs DQ4 12
write control
input
W 13
A5 14
address
inputs
A6 15
A7 16
A8 17
A9 18
Outline
36 NC
35 A18
34 A17
33 A16
address
inputs
32 A15 output enable
31 OE input
30 DQ8
29 DQ7
data
inputs/
outputs
28 GND(0V)
27 VCC (3.3V)
26 DQ6
25 DQ5
data
inputs/
outputs
24 A14
23 A13
22 A12
21 A11
address
inputs
20 A10
19 NC
36P0K (SOJ)
APPLICATION
High-speed memory units
BLOCK DIAGRAM
PACKAGE
36pin 400mil SOJ
address
inputs
A0 1
A1 2
A2 3
A3 4
A4 5
A5 14
A6 15
A7 16
A8 17
S6
W 13
OE 31
MEMORY ARRAY
512 ROWS
8192 COLUMNS
COLUMN I/O CIRCUITS
CCOOLLUUMMNNADDRESS
ADDDREECSOSDERS
DECODERS
COLUMN INPUT BUFFERS
7 DQ1
8 DQ2
11 DQ3
12 DQ4
25 DQ5
26 DQ6
29 DQ7
30 DQ8
data
inputs/
outputs
9 VCC (3.3V)
27
10
GND (0V)
28
18 20 21 22 23 24 32 33 34 35
A9 A10 A11A12 A13 A14 A15 A16 A16 A17
address inputs
MITSUBISHI
ELECTRIC
1
1 page  
MITSUBISHI LSIs
M5M5V4R08J-12,-15,-20
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
CAPACITANCE
(Ta=0
~
70
C,
Vcc=3.3V
+10%
-5%
unless
otherwise
noted)
Symbol
Parameter
Test Condition
CI Input capacitance
CO Output capacitance
V I =GND, V I =25mVrms,f=1MHz
V O=GND, VO=25mVrms,f=1MHz
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc=5V,Ta=25 C
3: CI,CO are periodically sampled and are not 100% tested.
Limit
Min Typ Max Unit
7 pF
8 pF
AC
ELECTRICAL
CHARACTERISTICS
(Ta=0
~ 70
C, Vcc=3.3V
+10%
-5%
unless otherwise noted)
(1)MEASUREMENT CONDITION
Input pulse levels •••••••••••••••••••••••• VIH =3.0V, VIL =0.0V
Input rise and fall time •••••••••••••••••••••••••••••••••••••• 3ns
Input timing reference levels •••••••••••• VIH =1.5V, VIL =1.5V
Output timing reference levels •••••••••• VOH=1.5V, VOL =1.5V
Output loads •••••••••••••••••••••••••••••••••••••••••• Fig1,Fig2
OUTPUT Z0=50Ω
RL=50Ω
VL=1.5V
Fig.1 Output load
Vcc
480Ω
DQ 5pF
255Ω (including
scope and JIG)
Fig.2 Output load for ten, t dis
MITSUBISHI
ELECTRIC
3
5 Page 
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet M5M5V4R08J-15.PDF ] | |
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