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PDF M5M5V416CWG-70HI Data sheet ( Hoja de datos )

Número de pieza M5M5V416CWG-70HI
Descripción 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Fabricantes Mitsubishi 
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No Preview Available ! M5M5V416CWG-70HI Hoja de datos, Descripción, Manual

2003.08.21 Ver. 7.0
www.DataSheet4U.com
RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5V416CWG is a f amily of low v oltage 4-Mbit static RAMs - Single 2.7~3.6V power supply
organized as 262144-words by 16-bit, f abricated by Renesas's - Small stand-by current: 0.2µA (3.00V, ty p.)
high-perf ormance 0.18µm CMOS technology .
- No clocks, No ref resh
The M5M5V416C is suitable f or memory applications where a
- Data retention supply v oltage =2.0V
simple interf acing , battery operating and battery backup are the - All inputs and outputs are TTL compatible.
important design objectiv es.
- Easy memory expansion by S1#, S2, BC1# and BC2#
M5M5V416CWG is packaged in a CSP (chip scale package),
- Common Data I/O
with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball) - Three-state outputs: OR-tie capability
and ball pitch of 0.75mm. It giv es the best solution f or
- OE# prev ents data contention in the I/O bus
a compaction of m ounting area as well as f lexibility of wiring
- Process technology : 0.18µm CMOS
pattern of printed circuit boards.
- Package: 48ball 7.0mm x 8.5mm CSP
Version,
Operating
temperature
Part name
I-version
-40 ~ +85°C
M5M5V416CWG -55HI
M5M5V416CWG -70HI
Power
Supply
Access time
max.
Stand-by c urrent (µA)
* Typical(3.0V)
Ratings (max. @3.6V)
25°C 40°C Voltage 25°C 40°C 70°C 85°C
Activ e
current
Icc1
(3.0V, ty p.)
2.7 ~ 3.6V
55ns
70ns
3.0V 1.0 2.0 10 20
30mA
0.2 0.4 3.3V 1.5 2.5 10
20
(10MHz)
5mA
3.6V 2.5 4.0 10 20 (1MHz)
PIN CONFIGURATION
* Typical parameter indicates the value for the center
of distribution, and not 100% tested.
(TOP VIEW)
1 23 456
A BC1# OE#
A0
A1
A2 S2
B DQ16 BC2#
A3
A4 S1# DQ1
C DQ14 DQ15
A5
A6 DQ2 DQ3
D GND DQ13
A17
A7 DQ4 VCC
E VCC
DQ12
NC or
GND
A16
DQ5 GND
F DQ11 DQ10 A14 A15 DQ7 DQ6
G DQ9
N.C. A12
A13 W#
DQ8
H N C A8 A9 A10 A11 N.C.
Outline: 48FJA
NC: No Connection
*Don't connect E3 ball to voltage level more than 0V.
Pin Function
A0 ~ A17 Address input
DQ1 ~ DQ16 Data input / output
S1# Chip select input 1
S2 Chip select input 2
W# Write control input
OE#
BC1#
Output enable input
Lower By te (DQ1 ~ 8)
BC2# Upper By te (DQ9 ~ 16)
Vcc Power supply
GND
Ground supply
1

1 page




M5M5V416CWG-70HI pdf
2003.08.21 Ver. 7.0
RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
tCR
A 0~17
ta(A)
tv (A)
BC1#,BC2#
(Note3)
ta(BC1) or ta(BC2)
tdis (BC1) or tdis (BC1)
(Note3)
S1#
(Note3)
ta(S1)
tdis (S1)
(Note3)
S2
(Note3)
OE#
W# = "H" lev el
(Note3)
DQ1~16
Write cycle (W# control mode )
ta(S2)
ta (OE)
ten (OE)
ten (BC1)
ten (BC2)
ten (S1)
ten (S2)
tCW
tdis (S2)
tdis (OE)
VALID DATA
(Note3)
(Note3)
A 0~17
BC1#,BC2#
S1#
S2
(Note3)
(Note3)
(Note3)
tsu (BC1) or tsu(BC2)
tsu (S1)
tsu (S2)
(Note3)
(Note3)
(Note3)
OE#
W#
DQ1~16
tsu (A)
tsu (A-WH)
tw (W)
tdis (W)
tdis(OE)
DATAIN
STABLE
tsu (D) th (D)
trec (W)
ten(OE)
ten (W)
5

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