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PDF M5M5V416BUG-70HI Data sheet ( Hoja de datos )
| Número de pieza | M5M5V416BUG-70HI | |
| Descripción | 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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revision-01, 17th July '00
M5M5V416BUG - 70H I
MITSUBISHI LSIs
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V416B is a f amily of low v oltage 4-Mbit static RAMs
organized as 262,144-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.25µm CMOS technology .
The M5M5V416B is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are the
important design objectiv es.
M5M5V416BUG is packaged in a CSP (chip scale package),
with the outline of 7mm x 8.5mm, ball matrix of 6 x 8 (48pin) and
ball pitch of 0.75mm. It giv es the best solution f or a compaction
of mounting area as well as f lexibility of wiring pattern of printed
circuit boards.
Those are summarized in the part name table below.
FEATURES
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,ty p.)
No clocks, No ref resh
Data retention supply v oltage =2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S1, S2, BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prev ents data contention in the I/O bus
Process technology : 0.25µm CMOS
Package: 48pin 7mm x 8.5mm CSP
Version,
Operating
temperature
Part name
I-v ersion
-40 ~ +85°C M5M5V416BUG -70HI
Power
Supply
2.7 ~ 3.6V
Access time
max.
Stand-by c urrent Icc(PD), Vcc=3.0V
Activ e
ty pical *
Ratings (max.)
current
Icc1
25°C 40°C 25°C 40°C 70°C 85°C (3.0V, ty p.)
70ns
0.3µA 1µA
1µA 3µA 15µA 30µA
50mA
(10MHz)
7mA
(1MHz)
* "ty pical" parameter is sampled, not 100% tested.
PIN CONFIGURATION (TOP VIEW)
1 23 4 56
A BC1 OE A0 A1 A2 S2
B DQ9 BC2 A3
A4 S1 DQ1
C DQ10 DQ11 A5
A6 DQ2 DQ3
D GND DQ12 A17 A7 DQ4 VCC
E VCC DQ13 GND A16 DQ5 GND
F DQ15 DQ14 A14 A15 DQ6 DQ7
G DQ16 N.C. A12 A13 W DQ8
H N.C. A8 A9 A10 A11 N.C.
Outline: 48FJA
NC: No Connection
Pin Function
A0 ~ A17 Address input
DQ1 ~ DQ16 Data input / output
S1 Chip select input 1
S2 Chip select input 2
W Write control input
OE
BC1
BC2
Vcc
Output enable input
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
Power supply
GND Ground supply
MITSUBISHI ELECTRIC
1
1 page  
revision-01, 17th July '00
M5M5V416BUG - 70H I
MITSUBISHI LSIs
(4)TIMING DIAGRAMS
Read cycle
A 0~17
BC1 ,BC2
S1
(Note3)
(Note3)
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
tCR
ta(A)
ta(BC1) or ta(BC2)
tv (A)
ta(S1)
tdis (BC1) or tdis (BC1)
tdis (S1)
(Note3)
(Note3)
S2
(Note3)
OE
W = "H" lev el
(Note3)
DQ1~16
Write cycle ( W control mode )
ta(S2)
ta (OE)
ten (OE)
ten (BC1)
ten (BC2)
ten (S1)
ten (S2)
tCW
tdis (S2)
tdis (OE)
VALID DATA
(Note3)
(Note3)
A 0~17
BC1,BC2
S1
S2
(Note3)
(Note3)
(Note3)
tsu (BC1) or tsu(BC2)
tsu (S1)
tsu (S2)
(Note3)
(Note3)
(Note3)
OE
W
DQ1~16
tsu (A)
tdis(OE)
tsu (A-WH)
tw (W)
tdis (W)
DATA IN
STABLE
tsu (D) th (D)
trec (W)
ten(OE)
ten (W)
MITSUBISHI ELECTRIC
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet M5M5V416BUG-70HI.PDF ] | |
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