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PDF M5M5V216AWG-70HI Data sheet ( Hoja de datos )

Número de pieza M5M5V216AWG-70HI
Descripción 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
Fabricantes Mitsubishi 
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No Preview Available ! M5M5V216AWG-70HI Hoja de datos, Descripción, Manual

revision-01, ' 98.12.08
M5M5V216AWG
MITSUBISHI LSIs
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5V216A is a family of low voltage 2-Mbit static RAMs
organized as 131,072-words by 16-bit, fabricated by Mitsubishi's
high-performance 0.25µm CMOS technology.
The M5M5V216A is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5V216AWG is packaged in a CSP (chip scale package),
with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48pin)
and ball pitch of 0.75mm. It gives the best solution for a
compaction of mounting area as well as flexibility of wiring pattern
of printed circuit boards.
From the point of operating temperature, the family is divided
into three versions; "Standard", "W-version", and "I-version".
Those are summarized in the part name table below.
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,typ.)
No clocks, No refresh
Data retention supply voltage=2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S , BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prevents data contention in the I/O bus
Process technology: 0.25µm CMOS
Package: 48 pin 7.0mm x8.5mm CSP
PART NAME TABLE
Version,
Operating
temperature
Part name
M5M5V216AWG -55L
Standard
0 ~ +70 C
M5M5V216AWG -70L
M5M5V216AWG -55H
M5M5V216AWG -70H
M5M5V216AWG -55LW
W-version
-20 ~ +85 C
M5M5V216AWG -70LW
M5M5V216AWG -55HW
M5M5V216AWG -70HW
M5M5V216AWG -55L I
I-version
-40 ~ +85 C
M5M5V216AWG -70L I
M5M5V216AWG -55H I
M5M5V216AWG -70H I
PIN CONFIGURATION
(TOP VIEW)
1 2 3456
A BC1 OE A6 A3 A0 NC
B
DQ
16
BC2
A7
A2
S
DQ
1
C
DQ DQ
14 15
A5
A1
DQ
2
DQ
3
D
GND
DQ
13
NC
A4
DQ
4
Vcc
E
Vcc
DQ
12
GND A16
DQ
5
GND
F
DQ DQ
11 10
A9
A14
DQ
7
DQ
6
G
DQ
9
NC
A10 A13
W
DQ
8
H NC A8 A11 A12 A15 NC
Power
Supply
Access
time
max.
Stand-by current Icc(PD), Vcc=3.0V
typical *
Ratings (max.)
25 C 40 C 25 C 40 C 70 C 85 C
Active
current
Icc1
(3.0V, typ.)
55ns(@ 2.7V) / 50ns(@3.3V)
2.7 ~ 3.6V
70ns(@ 2.7V) / 65ns(@3.3V)
---
---
--- --- 20µA ---
2.7 ~ 3.6V
2.7 ~ 3.6V
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
0.3µA 1µA
--- ---
1µA
---
3µA 8µA ---
45mA
--- 20µA 50µA (10MHz)
55ns(@ 2.7V) / 50ns(@3.3V)
2.7 ~ 3.6V 70ns(@ 2.7V) / 65ns(@3.3V) 0.3µA 1µA
55ns(@ 2.7V) / 50ns(@3.3V)
2.7 ~ 3.6V
70ns(@ 2.7V) / 65ns(@3.3V)
---
---
1µA
---
3µA 8µA 24µA
--- 20µA 50µA
5mA
(1MHz)
55ns(@ 2.7V) / 50ns(@3.3V)
2.7 ~ 3.6V
0.3µA 1µA
70ns(@ 2.7V) / 65ns(@3.3V)
1µA
3µA 8µA 24µA
* "typical" parameter is sampled, not 100% tested.
(BOTTOM VIEW)
65 4321
A NC A0 A3 A6 OE BC1
B
DQ
1
S
A2
A7
BC2
DQ
16
C
DQ DQ
32
A1
A5
DQ
15
DQ
14
D
Vcc
DQ
4
A4
NC
DQ
13
GND
E
GND
DQ
5
A16 GND
DQ
12
Vcc
F
DQ
6
DQ
7
A14 A9
DQ
10
DQ
11
G
DQ
8
W
A13 A10 NC
DQ
9
H NC A15 A12 A11 A8 NC
Pin Function
A0 ~ A16 Address input
DQ1 ~ DQ16 Data input / output
S
W
OE
BC1
BC2
Vcc
Chip select input
Write control input
Output inable input
Lower Byte (DQ1 ~ 8)
Upper Byte (DQ9 ~ 16)
Power supply
GND Ground supply
Outline: 48FJA
NC: No Connection
MITSUBISHI ELECTRIC
1

1 page




M5M5V216AWG-70HI pdf
revision-01, ' 98.12.08
M5M5V216AWG
MITSUBISHI LSIs
(4)TIMING DIAGRAMS
Read cycle
A0~16
BC1
and / or
BC2
S
OE
W = "H" level
DQ1~16
(Note3)
(Note3)
(Note3)
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
tCR
ta(A)
ta(BC1) or ta(BC2)
tv (A)
ta(S)
ta (OE)
ten (OE)
ten (BC1)
ten (BC2)
ten (S)
tdis (BC1) or tdis (BC1)
tdis (S)
tdis (OE)
VALID DATA
(Note3)
(Note3)
(Note3)
Write cycle ( W control mode )
tCW
A0~16
BC1
and / or
BC2
S
(Note3)
(Note3)
tsu (BC1) or tsu(BC2)
tsu (S)
tsu (A-WH)
(Note3)
(Note3)
OE
W
DQ1~16
tsu (A)
tdis(OE)
tw (W)
tdis (W)
DATA IN
STABLE
tsu (D) th (D)
trec (W)
ten(OE)
ten (W)
MITSUBISHI ELECTRIC
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