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PDF M5M5V208AKR Data sheet ( Hoja de datos )

Número de pieza M5M5V208AKR
Descripción 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
Fabricantes Mitsubishi 
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Revision-A0.2E 29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
DESCRIPTION
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
FEATURES
The M5M5V208A is a family of low voltage 2-Mbit static RAMs
organized as 262,144-words by 8-bit, fabricated by Mitsubishi's high-
performance 0.25µm CMOS technology.
The M5M5V208A is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
The M5M5V208A is packaged in 32-pin 8mm x 13.4mm STSOP
packages. Two types of STSOPs are available, M5M5V208AKV
(normal-lead-bend STSOP) and M5M5V208AKR (reverse-lead-bend
STSOP). These two types STSOPs are suitable for a surface
mounting on double-sided printed circuit boards.
From the point of operating temperature, the family is divided into
three versions; "Standard", "W-version", and "I-version". Those are
summarized in the part name table below.
• Single 2.7 ~ 3.6V power supply
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
• Easy memory expansion and power down by S1 & S2
• Data retention supply voltage=2.0V
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Common Data I/O
• Battery backup capability
• Small stand-by current • • • • • • • • • • 0.3µA(typ.)
PACKAGE
PART NAME TABLE
M5M5V208AKV,KR : 32pin 8 X 13.4 mm TSOP
Version,
Operating
temperature
Part name
(## stands for"KV"or"KR")
Power
Supply
Standard
0 ~ +70°C
M5M5V208A## -55L
M5M5V208A## -70L
M5M5V208A## -55H
M5M5V208A## -70H
2.7 ~ 3.6V
2.7 ~ 3.6V
M5M5V208A## -55LW
W-version M5M5V208A## -70LW 2.7 ~ 3.6V
-20
~
+85°C
M5M5V208A##
M5M5V208A##
-55HW
-70HW
2.7
~
3.6V
M5M5V208A## -55LI
I-version M5M5V208A## -70LI
-40
~
+85°C
M5M5V208A## -55HI
M5M5V208A## -70HI
2.7 ~ 3.6V
2.7 ~ 3.6V
Access
time
max.
55ns
70ns
55ns
70ns
55ns
70ns
55ns
70ns
55ns
70ns
55ns
70ns
Stand-by current Icc(PD), Vcc=3.0V
typical *
Ratings (max.)
25°C 40°C 25°C 40°C 70°C 85°C
Active
current
Icc1
(3.0V, typ.)
--- --- --- --- 20µA ---
0.3µA ---
--- ---
0.3µA ---
1µA 3µA 8µA --- 20mA
(f=10MHz)
--- --- 20µA 50µA
3mA
1µA 3µA 8µA 24µA (f=1MHz)
--- --- --- --- 20µA 50µA
0.3µA --- 1µA 3µA 8µA 24µA
* "typical" parameter is sampled, not 100% tested.
PIN CONFIGURATION (TOP VIEW)
A11 1
A9 2
A8 3
A13 4
W5
S2 6
A15 7
Vcc 8
A17 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
M5M5V208AKV
Outline 32P3K-B(KV)
32 OE
31 A10
30 S1
29 DQ8
28 DQ7
27 DQ6
26 DQ5
25 DQ4
24 GND
23 DQ3
22 DQ2
21 DQ1
20 A0
19 A1
18 A2
17 A3
A4 16
A5 15
A6 14
A7 13
A12 12
A14 11
A16 10
A17 9
Vcc 8
A15 7
S2 6
W5
A13 4
A8 3
A9 2
A11 1
M5M5V208AKR
Outline 32P3K-C(KR)
17 A3
18 A2
19 A1
20 A0
21 DQ1
22 DQ2
23 DQ3
24 GND
25 DQ4
26 DQ5
27 DQ6
28 DQ7
29 DQ8
30 S1
31 A10
32 OE
MITSUBISHI ELECTRIC
1

1 page




M5M5V208AKR pdf
Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
(4) TIMING DIAGRAMS
Read cycle
A0~17
S1
(Note 3)
S2
(Note 3)
OE
(Note 3)
DQ1~8
W = "H" level
Write cycle (W control mode)
A0~17
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
tCR
ta(A)
ta (S1)
ta (S2)
ta (OE)
ten (OE)
ten (S1)
ten (S2)
tCW
tv (A)
tdis (S1)
tdis (S2)
tdis (OE)
DATA VALID
(Note 3)
(Note 3)
(Note 3)
S1
S2
OE
W
DQ1~8
(Note 3)
(Note 3)
tsu (S1)
tsu (S2)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
tdis (OE)
tdis (W)
ten(OE)
ten (W)
DATA IN
STABLE
tsu (D) th (D)
(Note 3)
(Note 3)
MITSUBISHI ELECTRIC
5

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