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PDF M5M5V108DFP-70H Data sheet ( Hoja de datos )

Número de pieza M5M5V108DFP-70H
Descripción 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Fabricantes Mitsubishi 
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No Preview Available ! M5M5V108DFP-70H Hoja de datos, Descripción, Manual

7th.July.2000 Ver. 1.0
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
The M5M5V108DFP,VP,KV are a 1048576-bit CMOS static RAM
organized as 131072 word by 8-bit which are fabricated using high-
performance triple-polysilicon and double metal CMOS technology.
The use of thin film transistor (TFT) load cells and CMOS periphery
result in a high density and low power static RAM.
They are low standby current and low operation current and ideal
for the battery back-up application.
The M5M5V108DVP,KV are packaged in a 32-pin thin small
outline package which is a high reliability and high density surface
mount device(SMD).
FEATURES
Type name
M5M5V108DFP,VP,KV-70H
Access
time
(max)
VCC
Power supply current
Active stand-by
(1MHz)
(max)
(max)
70ns 2.7~3.6V 5mA 12µA
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S1,S2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
Package
M5M5V108DFP ············ 32pin 525mil SOP
M5M5V108DVP,RV ············ 32pin 8 X 20 mm2 TSOP
2
M5M5V108DKV,KR ············ 32pin 8 X 13.4 mm TSOP
APPLICATION
Small capacity memory units
PIN CONFIGURATION (TOP VIEW)
ADDRESS
INPUTS
DATA
INPUTS/
OUTPUTS
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
GND 16
32 VCC
31
A15
ADDRESS
INPUT
S30
2
CHIP SELECT
INPUT
W29
WRITE CONTROL
INPUT
28 A13
27 A8
26 A9
ADDRESS
INPUTS
25 A11
24
OE OUTPUT ENABLE
INPUT
23
A10
ADDRESS
INPUT
S22
1
CHIP SELECT
INPUT
21 DQ8
20 DQ7
19 DQ6
18 DQ5
DATA
INPUTS/
OUTPUTS
17 DQ4
Outline 32P2M-A
A11 1
A9 2
A8 3
A13 4
W5
S2 6
A15 7
VCC 8
NC 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
M5M5V108DVP,KV
32 OE
31 A10
30 S1
29 DQ8
28 DQ7
27 DQ6
26 DQ5
25 DQ4
24 GND
23 DQ3
22 DQ2
21 DQ1
20 A0
19 A1
18 A2
17 A3
Outline 32P3H-E(VP), 32P3K-B(KV)
MITSUBISHI
ELECTRIC
NC : NO CONNECTION
1

1 page




M5M5V108DFP-70H pdf
(4) TIMING DIAGRAMS
Read cycle
A0~16
S1
S2
OE
DQ1~8
W = "H" level
(Note 3)
(Note 3)
(Note 3)
7th.July.2000 Ver. 1.0
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
tCR
ta(A)
ta (S1)
ta (S2)
ta (OE)
ten (OE)
ten (S1)
ten (S2)
tv (A)
tdis (S1)
tdis (S2)
tdis (OE)
DATA VALID
(Note 3)
(Note 3)
(Note 3)
Write cycle (W control mode)
A0~16
tCW
S1
S2
OE
W
DQ1~8
(Note 3)
(Note 3)
tsu (S1)
tsu (S2)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
tdis (OE)
tdis (W)
ten (W)
ten(OE)
DATA IN
STABLE
tsu (D)
th (D)
MITSUBISHI
ELECTRIC
(Note 3)
(Note 3)
5

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