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PDF M5M54R04AJ-12 Data sheet ( Hoja de datos )
| Número de pieza | M5M54R04AJ-12 | |
| Descripción | 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de M5M54R04AJ-12 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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1998.11.30 Ver.B
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
MITSUBISHI LSIs
M5M54R04AJ-10,-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M54R04AJ is a family of 1048576-word by 4-bit
static RAMs, fabricated with the high performance CMOS
silicon gate process and designed for high speed
application.
These devices operate on a single 3.3V supply, and are
directly TTL compatible. They include a power down
feature as well.
FEATURES
•Fast access time
M5M54R04AJ-10 ... 10ns(max)
M5M54R04AJ-12 ... 12ns(max)
M5M54R04AJ-15 ... 15ns(max)
•Single +3.3V power supply
•Fully static operation : No clocks, No refresh
•Common data I/O
•Easy memory expansion by S
•Three-state outputs : OR-tie capability
•OE prevents data contention in the I/O bus
•Directly TTL compatible : All inputs and outputs
A0 1
A1 2
aindpduretsss
A2 3
A3 4
chip select
input
A4 5
S6
data inputs/
outputs(3.3V)
DQ1
VCC
7
8
(0V) GND 9
data inputs/
outputs
DQ2 10
write control W 11
input
A5 12
A6 13
address
inputs
A7 14
A8 15
A9 16
Outline
32 A19
31 A18
30 A17
29 A16
aindpduretsss
28 A15
27 OE
output enable
input
26 DQ4 data inputs/
25 GND (0V) outputs
24 VCC (3.3V)
23 DQ3
22 A14
data inputs/
outputs
21 A13
20 A12
19 A11
address
inputs
18 A10
17 NC
32P0K(SOJ)
APPLICATION
High-speed memory units
BLOCK DIAGRAM
PACKAGE
M5M54R04AJ
: 32pin 400mil SOJ
adress
inputs
A0 1
A1 2
A2 3
A3 4
A4 5
A5 12
A6 13
A7 14
A8 15
A9 16
MEMORY ARRAY
1024 ROWS
4096 COLUMNS
7 DQ1
10 DQ2
23 DQ3
26 DQ4
data
inputs/
outputs
S6
W 11
OE 27
COLUMN I/O CIRCUITS
COLUMN ADDRESS
DECODERS
COLUMN INPUT BUFFERS
8
VCC (3.3V)
24
9
GND(0V)
25
18 19 20 21 22 28 29 30 31 32
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
address inputs
MITSUBISHI
ELECTRIC
1
1 page  
MITSUBISHI LSIs
M5M54R04AJ-10,-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
A 0~19
VIH
VIL
DQ1~4 VOH
VOL
tv(A)
PREVIOUS DATA VALID
W=H
S=L
OE=L
t CR
ta(A)
UNKNOWN
tv(A)
DATA VALID
Read cycle 2 (Note 3)
VIH
S VIL
t CR
ta(S)
(Note 4)
ten(S)
(Note 4)
tdis(S)
DQ1~4
VOH
VOL
ICC1
Icc
ICC2
UNKNOWN
tPU
50%
DATA VALID
tPD
50%
W=H
OE=L
Note 3. Addresses valid prior to or coincident with S transition low.
4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 5)
VIH
OE VIL
t CR
ta(OE)
(Note 4)
tdis(OE)
(Note 4) ten(OE)
DQ1~4
VOH
VOL
W=H
S=L
UNKNOWN
DATA VALID
Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI
ELECTRIC
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet M5M54R04AJ-12.PDF ] | |
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