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PDF M5M54R01AJ-15 Data sheet ( Hoja de datos )
| Número de pieza | M5M54R01AJ-15 | |
| Descripción | 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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1998.11.30 Ver.B
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
MITSUBISHI LSIs
M5M54R01AJ-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M54R01AJ is a family of 4194304-word by 1-bit
static RAMs, fabricated with the high performance CMOS
silicon gate process and designed for high speed
application.
These devices operate on a single 3.3V supply, and are
directly TTL compatible. They include a power down
feature as well.
FEATURES
•Fast access time
M5M54R01AJ-12 ... 12ns(max)
M5M54R01AJ-15 ... 15ns(max)
•Single +3.3V power supply
•Fully static operation : No clocks, No refresh
•Easy memory expansion by S
•Three-state outputs : OR-tie capability
•OE prevents data contention in the I/O bus
•Directly TTL compatible : All inputs and outputs
A0 1
A1 2
address
A2 3
inputs
A3 4
A4 5
chip select
input
A5 6
S7
(3.3V) VCC 8
(0V) GND 9
data inputs D 10
write control W 11
input
A6 12
address
inputs
A7 13
A8 14
A9 15
A10 16
Outline
32P0K
32 A21
31 A20
30 A19
address
29 A18 inputs
28 A17
27 A16
26 OE
output enable
input
25 GND (0V)
24 VCC (3.3V)
23 Q data outputs
22 A15
21 A14
20 A13
19 A12
address
inputs
18 A11
17
B1/B4
byte control
input
APPLICATION
High-speed memory units
BLOCK DIAGRAM
address
inputs
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 12
A7 13
A8 14
A9 15
S7
W 11
OE 26
B1/B4 17
PACKAGE
M5M54R01AJ
: 32pin 400mil SOJ
MEMORY ARRAY
1024 ROWS
4096 COLUMNS
23
Q
data
outputs
COLUMN I/O CIRCUITS
COLUMNCOLUMN ADDRESS
ADDRESS DECODERS
DECODERS
COLUMN INPUT BUFFERS
16 18 19 20 21 22 27 28 29 30 31 32
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
address inputs
10
D
data
inputs/
8 VCC (3.3V)
24
9
GND(0V)
25
MITSUBISHI
ELECTRIC
1
1 page  
MITSUBISHI LSIs
M5M54R01AJ-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
A 0~21
VIH
VIL
tv(A)
Q
VOH
PREVIOUS DATA VALID
VOL
W=H
S=L
OE=L
t CR
ta(A)
UNKNOWN
tv(A)
DATA VALID
Read cycle 2 (Note 3)
VIH
S VIL
t CR
ta(S)
(Note 4)
ten(S)
(Note 4)
tdis(S)
Q VOH
VOL
ICC1
Icc
ICC2
UNKNOWN
tPU
50%
DATA VALID
tPD
50%
W=H
OE=L
Note 3. Addresses valid prior to or coincident with S transition low.
4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 5)
VIH
OE VIL
t CR
ta(OE)
(Note 4)
tdis(OE)
(Note 4) ten(OE)
Q VOH
VOL
W=H
S=L
UNKNOWN
DATA VALID
Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI
ELECTRIC
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet M5M54R01AJ-15.PDF ] | |
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