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PDF M5M51R16AWG-12HI Data sheet ( Hoja de datos )

Número de pieza M5M51R16AWG-12HI
Descripción 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
Fabricantes Mitsubishi 
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MITSUBISHI LSIs
M5M51R16AWG -10LI, -12LI, -15LI,
-10HI, -12HI, -15HI
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M51R16AWG is a 1048576-bit CMOS static RAM
organized as 65536 words by 16-bits, which are fabricated using
high-performance CMOS technology. The use of CMOS cells and
periphery results in a high density and low power static RAM.
The M5M51R16AWG can achieve low stand-by current and low
operation current and ideal for the battery back-up application.
The M5M51R16AWG is packaged in a 48-pin chip scale package
which is a high reliability and high density surface mount device
(SMD). Using this type of devices, it becomes very easy to design
a small system.
The M5M51R16AWG is fully compatible with the M5M51R16WG.
FEATURE
Type name
M5M51R16AWG- 10LI
M5M51R16AWG- 12LI
M5M51R16AWG- 15LI
M5M51R16AWG- 10HI
M5M51R16AWG- 12HI
M5M51R16AWG- 15HI
Power supply current
Access time
(max)
Active Stand-by
(max) (max)
100ns
120ns
150ns
100ns
120ns
150ns
10mA
(1MHz)
4µA
2µA
• Single +1.8V~2.7V power supply
• Low power down current 0.05µA(typ.)
• Directly TTL compatible : All inputs and outputs
• Easy memory expansion and power down by S,BC1 and BC2
• Data hold on +1.0V power supply
• Three-state outputs : OR-tie capability
• OE prevents data contention in the I/O bus
• Common data I/O
• Separate control of lower and upper bytes by BC1 and BC2
• Package
48-pin chip scale package(CSP)
Ball pitch : 0.75mm
Package size: 7.0mm x 8.5mm
APPLICATION
Small capacity memory units.
123456
A
BC1 OE A6
B
DQ16 BC2 A7
C
DQ14 DQ15 A5
D
GND DQ13 NC
A3 A0 NC
A2 S DQ1
A1 DQ2 DQ3
A4 DQ4 VCC
E
VCC DQ12 GND NC DQ5 GND
F
DQ11 DQ10 A9
A14 DQ7 DQ6
G
DQ9 NC A10 A13 W DQ8
H
NC A8 A11 A12 A15 NC
PIN CONFIGURATION (BOTTOM VIEW)
654321
A
NC A0 A3 A6 OE BC1
B
DQ1 S A2 A7 BC2 DQ16
C
DQ3 DQ2 A1 A5 DQ15 DQ14
D
VCC DQ4 A4 NC DQ13 GND
E
GND DQ5 NC GND DQ12 VCC
F
DQ6 DQ7 A14 A9 DQ10 DQ11
G
DQ8 W A13 A10 NC DQ9
H
NC A15 A12 A11 A8 NC
Outline 48FJA
Aug.1. 1998
MITSUBISHI
ELECTRIC
NC : NO CONNECTION
1

1 page




M5M51R16AWG-12HI pdf
MITSUBISHI LSIs
M5M51R16AWG -10LI, -12LI, -15LI,
-10HI, -12HI, -15HI
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
A0~15
BC1 and/or BC2
S
OE
DQ1~16
tCR
(Note 4)
ta(A)
ta(BC1) or
ta(BC2)
(Note 4)
ta(S)
ta(OE)
ten(OE)
(Note 4)
ten(BC1)
ten(BC2)
ten(S)
W = "H" level
tv(A)
tdis(BC1) or
tdis(BC2)
tdis(S)
tdis(OE)
DATA VALID
Write cycle ( W control mode )
A0~15
tCW
BC1 and/or BC2
S
OE
(Note 4)
(Note 4)
tsu(BC1) or tsu(BC2)
tsu(S)
tsu(A-WH)
W
DQ1~16
Aug.1. 1998
tsu(A)
tw(W)
trec(W)
tdis(OE)
tdis(W)
ten(OE)
ten(W)
DATA IN
STABLE
tsu(D) th(D)
MITSUBISHI
ELECTRIC
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
5

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