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PDF M5M4V64S20ATP-10 Data sheet ( Hoja de datos )

Número de pieza M5M4V64S20ATP-10
Descripción 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
Fabricantes Mitsubishi 
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No Preview Available ! M5M4V64S20ATP-10 Hoja de datos, Descripción, Manual

SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S20ATP-8, -10, -12
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
PIN CONFIGURATION
(TOP VIEW)
The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit
Synchronous DRAM, with LVTTL interface. All inputs and
Vdd 1
NC 2
outputs are referenced to the rising edge of CLK. The
VddQ 3
NC 4
54 Vss
53 NC
52 VssQ
51 NC
M5M4V64S20ATP achieves very high speed data rate up to
125MHz, and is suitable for main memory or graphic memory
in computer systems.
DQ0
VssQ
NC
NC
VddQ
NC
5
6
7
8
9
10
50 DQ3
49 VddQ
48 NC
47 NC
46 VssQ
45 NC
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 125MHz / 100MHz / 83MHz
DQ1
VssQ
NC
Vdd
NC
/WE
11
12
13
14
15
16
44 DQ2
43 VddQ
42 NC
41 Vss
40 NC (Vref)
39 DQM
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8 (programmable)
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
17
18
19
20
21
22
23
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
- Burst type- sequential / interleave (programmable)
- Column access - random
- Auto precharge / All bank precharge controlled by A10
A1 24
A2 25
A3 26
Vdd 27
31 A6
30 A5
29 A4
28 Vss
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A9
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with
0.8mm lead pitch
M5M4V64S20ATP-8
M5M4V64S20ATP-10
M5M4V64S20ATP-12
Max.
Frequency
125MHz
100MHz
83MHz
CLK Access
Time
6ns
8ns
8ns
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-3
DQM
A0-11
BA0,1
Vdd
VddQ
Vss
VssQ
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Output Disable/ Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
1

1 page




M5M4V64S20ATP-10 pdf
SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S20ATP-8, -10, -12
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
Deselect
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto-
Precharge
Auto-Refresh
Self-Refresh Entry
DESEL
NOP
ACT
PRE
PREA
WRITE
WRITEA
READ
READA
REFA
REFS
Self-Refresh Exit
REFSX
Burst Terminate
Mode Register Set
TERM
MRS
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
CKE
n
X
X
X
X
X
X
X
X
X
H
L
H
H
X
X
/CS /RAS /CAS /WE BA0,1 A11
HX XXXX
LH HHXX
L L HHVV
L L HLVX
L L H L XX
LHL
LVX
LHL
LVX
LH L HVX
LH L HVX
L L L HXX
L L L HXX
HX XXXX
LH HHXX
LHHLXX
LLL LLL
A10 A0-9
XX
XX
VV
LX
HX
LV
HV
LV
HV
XX
XX
XX
XX
XX
L V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
MITSUBISHI ELECTRIC
5

5 Page





M5M4V64S20ATP-10 arduino
SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S20ATP-8, -10, -12
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MODE
REGISTER
SET
MRS
IDLE
REFA
AUTO
REFRESH
CKEL
CLK
SUSPEND
CKEH
ACT
CKEL
POWER
DOWN
CKEH
WRITE
ROW
ACTIVE
READ
CKEL
WRITE
SUSPEND
WRITE
CKEH
WRITEA READA
READ
WRITE
READ
CKEL
READ
SUSPEND
CKEH
WRITEA
CKEL
WRITEA
SUSPEND
WRITEA
CKEH
WRITEA
READA
PRE
PRE
PRE
READA
CKEL
READA
READA
SUSPEND
CKEH
POWER
APPLIED
POWER
ON
PRE
PRE
CHARGE
MITSUBISHI ELECTRIC
Automatic Sequence
Command Sequence
11

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