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PDF M5M4V16G50DFP-12 Data sheet ( Hoja de datos )
| Número de pieza | M5M4V16G50DFP-12 | |
| Descripción | 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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SGRAM (Rev. 0.0)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
PRELIMINARY
Some of contents are described for general products
and are subject to change without notice.
DESCRIPTION
The M5M4V16G50DFP is a 2-bank x 262,144-word x 32-bit Synchronous GRAM,
with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M5M4V16G50DFP can operate at frequencies of 100+ MHz. The
BLOCK WRITE and WRITE-PER-BIT functions provide improved performance
in graphic memory systems.
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequencies of 125 MHz
- Fully synchronous operation referenced to clock rising edge
- Dual bank operation controlled by A10(Bank Address)
- Internal pipelined operation: column address can be changed every clock cycle
- Programmable /CAS Latency (LVTTL: 2 and 3)
- Programmable Burst Length (1/2/4/8 and Full Page)
- Programmable Burst Type (Sequential / Interleave)
- Byte control using DQM0 - DQM3 signals in both read and write cycles
- Persistent Write-Per-Bit (WPB) function
- 8 Column Block Write (BW) function
- Auto Precharge / All bank precharge controlled by A9
- Auto Refresh and Self Refresh Capability
- 2048 refresh cycles /32ms
- LVTTL Interface
- 100 pin QFP package with 0.65mm lead pitch
Max.
CLK Access
Frequency
Time
M5M4V16G50DFP - 8 125MHz
7ns
M5M4V16G50DFP- 10
M5M4V16G50DFP- 12
100MHz
83MHz
8ns
10ns
MITSUBISHI ELECTRIC
1 page  
SGRAM (Rev. 0.0)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
BASIC FUNCTIONS
The M5M4V16G50DFP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS, /WE, and DSF at CLK rising edge. In
addition to 3 signals, /CS ,CKE and A9 are used as chip select, refresh option, and precharge option,
respectively.
For a more detailed definition of commands, please see the command truth table.
CLK
/CS
/RAS
/CAS
/WE
DSF
CKE
A9
Chip Select : L=select, H=deselect
Command
Command
Command
define basic commands
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate (ACT) [/CS, /RAS, DSF = L, /CAS, /WE = H]
ACT command activates a row in an idle bank indicated by A10 (BA) and row address
selected by A0 - A9.
Activate with WPB enable (ACTWPB) [/CS, /RAS = L, /CAS, /WE, DSF = H]
This command is the same as Activate except that Write-Per-Bit (WPB) is enabled. The Mask
Register’s contents are used as the WPB data.
Read (READ) [/CS, /CAS, DSF = L, /RAS, /WE = H]
READ command starts burst read from the active bank indicated by A10 (BA). First output data
appears after /CAS latency. When A9 = H at this command, the bank is deactivated after the burst read
(auto-precharge, READA).
Write (WRITE) [/CS, /CAS, /WE, DSF = L, /RAS = H]
WRITE command starts burst write to the active bank indicated by A10 (BA). Total data length to be
written is set by burst length. When A9 = H at this command, the bank is deactivated after the burst
write (auto-precharge, WRITEA).
Precharge (PRE) [/CS, /RAS, /WE, DSF = L, /CAS = H]
PRE command deactivates the active bank indicated by A10 (BA). This command also terminates
burst read /write operation. When A9 = H at this command, both banks are deactivated
(precharge all, PREA).
MITSUBISHI ELECTRIC
5 Page 
SGRAM (Rev. 0.0)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE DSF Address
PRE -
CHARGING
H
L
L
XX
HH
HH
X XX
H LX
L L BA
L H L H L BA, CA, A9
L H L L L BA, CA, A9
L H L L H BA, CA, A9
L L H H L BA, RA
L L H H L BA, RA
L L H L L BA, A9
L
L
L
ROW
H
ACTIVATING L
LL
LL
LL
XX
HH
H LX
L
Op-Code,
H Mode-Add
Op-Code,
L L Mode-Add
X XX
H LX
L H H L L BA
L H L H L BA, CA, A9
L H L L L BA, CA, A9
L H L L H BA, CA, A9
L L H H L BA, RA
L L H H H BA, RA
L L H L L BA, A9
L L L H LX
L
LL
L
Op-Code,
H Mode-Add
Op-Code,
L L L L L Mode-Add
Command
Action
DESEL NOP (Idle after tRP)
NOP
TERM
NOP (Idle after tRP)
ILLEGAL*2
READ / READA ILLEGAL*2
WRITE / WRITEA ILLEGAL*2
BW / BWA ILLEGAL*2
ACT
ILLEGAL*2
ACTWPB ILLEGAL*2
PRE / PREA NOP*4 (Idle after tRP)
REFA
ILLEGAL
SRS
ILLEGAL
MRS
ILLEGAL
DESEL NOP (Row Active after tRCD)
NOP
NOP (Row Active after tRCD)
TERM
ILLEGAL*2
READ / READA ILLEGAL*2
WRITE / WRITEA ILLEGAL*2
BW / BWA ILLEGAL*2
ACT
ACTWPB
PRE / PREA
REFA
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL
SRS
ILLEGAL
MRS
ILLEGAL
MITSUBISHI ELECTRIC
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M5M4V16G50DFP-12.PDF ] | |
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