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PDF M5M44800CTP-7S Data sheet ( Hoja de datos )

Número de pieza M5M44800CTP-7S
Descripción FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Fabricantes Mitsubishi 
Logotipo Mitsubishi Logotipo



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No Preview Available ! M5M44800CTP-7S Hoja de datos, Descripción, Manual

MITMSIUTBSIUSBHIISHLSI ILsSIs
M5MM5M444488000C0JC,TPJ-,5T,-6P,--75,-5,-S6,-,6-S7,-,7S
-5S,-6S,-7S
FAFSATSPTAPGAEGMEOMDOED4E19441390443-0B4I-TB(I5T2(45228482-8W8-OWRODRBDYB8Y-B8I-TB)IDT)YDNYANMAICMIRCARMAM
DESCRIPTION
This is a family of 524288-word by 8-bit dynamic RAMs, fabricated
with the high performance CMOS process, and is ideal for large-
capacity memory systems where high speed, low power
dissipation, and low costs are essential.
The use of double-layer metalization process technology and a
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application.
FEATURES
Type name
RAS CAS Address OE
access access access access
time time time time
Cycle
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M44800CXX-5,-5S 50 13 25 13
90 450
M5M44800CXX-6,-6S 60 15 30 15 110 375
M5M44800CXX-7,-7S 70 20 35 20 130 325
XX=J,TP
Standard 28pin SOJ, 28pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
CMOS lnput level
5.5mW (Max)
CMOS Input level
550µW (Max) *
Operating power dissipation
M5M44800Cxx-5,-5S
495mW (Max)
M5M44800Cxx-6,-6S
413mW (Max)
M5M44800Cxx-7,-7S
358mW (Max)
Self refresh capability *
Self refresh current
150µA(Max)
Extended refresh capability
Extended refresh current
150µA(Max)
Fast page mode(1024-column random access),Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, CAS and OE to control output buffer impedance
1024 refresh cycles every 16.4ms (A0 ~A9)
1024 refresh cycles every 128ms (A0 ~A9) *
* :Applicable to self refresh version (M5M44800CJ,TP-5S,-6S,-7S
:option) only
APPLICATION
Microcomputer memory, Refresh memory for CRT
PIN CONFIGURATION (TOP VIEW)
(5V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
NC 6
W7
RAS 8
A9 9
A0 10
A1 11
A2 12
A3 13
(5V)VCC 14
28 VSS(0V)
27 DQ8
26 DQ7
25 DQ6
24 DQ5
23 CAS
22 OE
21 NC
20 A8
19 A7
18 A6
17 A5
16 A4
15 VSS(0V)
Outline 28P0K(400mil SOJ)
(5V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
NC 6
W7
RAS 8
A9 9
A0 10
A1 11
A2 12
A3 13
(5V)VCC 14
28 VSS(0V)
27 DQ8
26 DQ7
25 DQ6
24 DQ5
23 CAS
22 OE
21 NC
20 A8
19 A7
18 A6
17 A5
16 A4
15 VSS(0V)
Outline 28P3Y-H(400mil TSOP Normal Bend)
NC:NO CONNECTION
PIN DESCRIPTION
Pin name
A0~A9
DQ1~DQ8
RAS
CAS
W
OE
Vcc
Vss
Function
Address inputs
Data inputs/outputs
Row address strobe input
Column address strobe input
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
1
M5M44800CJ,TP-5,-5S:Under development

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M5M44800CTP-7S pdf
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Fast-Page Mode Cycles)
(Ta=0~70˚C, VCC = 5V±10%, VSS=0V, unless otherwise noted, see notes 6,13,14)
Symbol
Parameter
Limits
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Min Max Min Max Min Max
Unit
tREF Refresh cycle time
16.4 16.4 16.4 ms
tREF Refresh cycle time *
128 128
128 ms
tRP RAS high pulse width
30 40 50
ns
tRCD
Delay time, RAS low to CAS low
(Note 15) 18 37 20 45 20 50 ns
tCRP Delay time, CAS high to RAS low
5 5 5 ns
tRPC Delay time, RAS high to CAS low
0 0 0 ns
tCPN CAS high pulse width
10 10 10
ns
tRAD Column address delay time from RAS low
(Note 16) 13 25 15 30 15 35 ns
tASR Row address setup time before RAS low
0 0 0 ns
tASC Column address setup time before CAS low (Note 17) 0 7 0 10 0 10 ns
tRAH Row address hold time after RAS low
8 10 10
ns
tCAH Column address hold time after CAS low
13 15 15
ns
tDZC
tDZO
tCDD
tODD
tT
Delay time, data to CAS low
Delay time, data to OE low
Delay time, CAS high to data
Delay time, OE high to data
Transition time
(Note 18) 0 0 0 ns
(Note 18) 0 0 0 ns
(Note 19) 13 15 20
ns
(Note 19) 13 15 20
ns
(Note 20) 1 50 1 50
1 50
ns
Note 13: The timing requirements are assumed tT=5ns.
Note 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Note 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
Note 16: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA.
Note 17: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC.
Note 18: Either tDZC or tDZO must be satisfied.
Note 19: Either tCDD or tODD must be satisfied.
Note 20: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS RAS low pulse width
tCAS CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read Setup time before CAS low
tRCH
Read hold time after CAS high
tRRH
Read hold time after RAS high
tRAL Column address to RAS hold time
tOCH
CAS hold time after OE low
tORH
RAS hold time after OE low
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Limits
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Min Max Min Max Min Max
90 110 130
50 10000 60 10000 70 10000
13 10000
50
15 10000
60
20 10000
70
13 15 20
000
(Note 21) 0 0 0
(Note 21) 0 0 0
25 30 35
13 15 20
13 15 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
M5M44800CJ,TP-5,-5S:Under development

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M5M44800CTP-7S arduino
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
RAS
VIH
VIL
CAS
VIH
VIL
A0~A9
VIH
VIL
VIH
W
VIL
DQ1~DQ8
(INPUTS)
VIH
VIL
DQ1~DQ8 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRAS
tRWC
tRP
tCRP
tRCD
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tRCS
tCSH
tRSH
tCAS
tCRP
tCAH
COLUMN
ADDRESS
tAWD
tCWD
tRWD
tCWL
tRWL
tWP
tASR
ROW
ADDRESS
Hi-Z
tDZC
tDS tDH
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
DATA
VALID
tOEA
tODD
tOEZ
DATA VALID
tOEH
Hi-Z
11
M5M44800CJ,TP-5,-5S:Under development

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