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PDF M5M44405CJ Data sheet ( Hoja de datos )

Número de pieza M5M44405CJ
Descripción EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Fabricantes Mitsubishi 
Logotipo Mitsubishi Logotipo



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MITMSIUTSBUISBHISI LHSI ILsSIs
M5M44405CJM,T5MP4-4540,-56C,J-,T7P,--55,-S6,,-7-,6-5SS,,--67SS,-7S
EDOED(OHY( PHEYRPEPRAGPAEGMEOMDOED) E41)9441390443-0B4IT-B(IT10(4180547865-7W6O-WRODRBDYB4Y-B4IT-B)ITDY) NDAYNMAICMRICARMAM
DESCRIPTION
This is a family of 1048576-word by 4-bit dynamic RAMs, fabricated
with the high performance CMOS process,and is ideal for large-
capacity memory systems where high speed, low power dissipation,
and low costs are essential.
The use of quadruple-layer polysilicon process combined with
silicide technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density at reduced costs.
Multiplexed address inputs permit both a reduction in pins and an
increase in system densities.
Self or extended refresh current is low enough for battery back-up
application.
PIN CONFIGURATION (TOP VIEW)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
FEATURES
Type name
RAS
access
time
(max.ns)
CAS
access
time
(max.ns)
Address
access
time
(max.ns)
OE
access
time
(max.ns)
Cycle
time
(min.ns)
Power
dissipa-
tion
(typ.mW)
M5M44405CXX-5,-5S 50 13 25 13
90 500
M5M44405CXX-6,-6S 60 15 30 15 110 400
M5M44405CXX-7,-7S 70 20 35 20 130 350
XX=J,TP
Standard 26 pin SOJ, 26 pin TSOP(II)
Single 5V±10%supply
Low stand-by power dissipation
CMOS lnput level
5.5mW (Max) *
CMOS lnput level
550µW (Max)
Low operating power dissipation
M5M44405Cxx-5,-5S
687.5mW (Max)
M5M44405Cxx-6,-6S
550.0mW (Max)
M5M44405Cxx-7,-7S
467.5mW (Max)
Self refresh capabiility *
Self refresh current
120µA(max)
Extended refresh capability *
Extended refresh current
120µA(max)
Hyper-page mode (1024-bit random access), Read-modify- write,
RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR
self refresh(-5S,-6S,-7S) capabilities
Early-write mode and OE and W to control output buffer impedance
All inputs, output TTL compatible and low capacitance
1024 refresh cycles every 16.4ms (A0~A9)
1024refresh cycle every 128ms (A0~A9) *
4-bit parallel test mode capability
* : Applicable to self refresh version (M5M44405CJ,TP-5S,-6S,-7S
: option) only
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh
memory for CRT, Frame Buffer memory for CRT
PIN DESCRIPTION
Pin name
Function
A0~A9
Address Inputs
DQ1~DQ4 Data Inputs / Outputs
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+5V)
1 Vss
Ground (0V)
M5M44405CJ,TP-5,-5S:Under development
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P0J (300mil SOJ)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P3Z-E (300mil TSOP)

1 page




M5M44405CJ pdf
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70˚C, VCC= 5V±10%, VSS=0V, unless otherwise noted, see notes 14,15)
Limits
Symbol
Parameter
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S Unit
Min Max Min Max Min Max
tREF Refresh cycle time
16.4 16.4 16.4 ms
tREF Refresh cycle time *
128 128 128 ms
tRP RAS high pulse width
tRCD Delay time, RAS low to CAS low
30 40 50
ns
(Note 16) 18
37 20
45 20
50
ns
tCRP Delay time, CAS high to RAS low
tRPC Delay time, RAS high to CAS low
tCPN CAS high pulse width
5 55
0 00
8 10 13
ns
ns
ns
tRAD Column address delay time from RAS low
(Note 17) 13
25 15
30 15
35
ns
tASR Row address setup time before RAS low
0 00
ns
tASC Column address setup time before CAS low (Note 18) 0 10 0 13 0 13 ns
tRAH Row address hold time after RAS low
tCAH Column address hold time after CAS low
8 10 10
8 10 10
ns
ns
tDZC Delay time, data to CAS low
tDZO Delay time, data to OE low
tRDD Delay time, RAS high to data
(Note 19) 0 0 0
(Note 19) 0 0 0
(Note 20) 13 15 20
ns
ns
ns
tCDD Delay time, CAS high to data
(Note 20) 13 15 20
ns
tODD
Delay time, OE high to data
(Note 20) 13 15 20
ns
tT Transition time
(Note 21) 1 50 1 50 1 50 ns
Note 14 : The timing requirements are assumed tT=2ns.
Note 15 : VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Note 16 : tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
Note 17 : tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA.
Note 18 : tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC.
Note 19 : Either tDZC or tDZO must be satisfied.
Note 20 : Either tRDD or tCDD or tODD must be satisfied.
Note 21 : tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS RAS low pulse width
tCAS CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read Setup time before CAS low
tRCH Read hold time after CAS high
tRRH Read hold time after RAS high
tRAL Column address to RAS hold time
tCAL Column address to CAS hold time
tORH
RAS hold time after OE low
tOCH
CAS hold time after OE low
Note 22 : Either tRCH or tRRH must be satisfied for a read cycle.
Limits
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Min Max Min Max Min Max
90 110 130
50 10000 60 10000 70 10000
8 10000 10 10000 13 10000
40 48 55
13 15 20
0 00
(Note 22) 0
00
(Note 22) 0
00
25 30 35
13 18 23
13 15 20
13 15 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
M5M44405CJ,TP-5,-5S:Under development

5 Page





M5M44405CJ arduino
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Early Write Cycle
RAS
CAS
A0~A9
VIH
VIL
VIH
VIL
VIH
VIL
tCRP
tRCD
tASR
tRAH
ROW
ADDRESS
tASC
tWC
tRAS
tCSH
tCAH
COLUMN
ADDRESS
tRSH
tCAS
VIH
W
VIL
DQ1~DQ4
(INPUTS)
VIH
VIL
tWCS
tWCH
tDS tDH
DATA VALID
tRP
tCRP
tASR
ROW
ADDRESS
DQ1~DQ4 VOH
(OUTPUTS) VOL
Hi-Z
VIH
OE
VIL
11
M5M44405CJ,TP-5,-5S:Under development

11 Page







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