|
|
PDF M5M44260CTP-6S Data sheet ( Hoja de datos )
| Número de pieza | M5M44260CTP-6S | |
| Descripción | FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M5M44260CTP-6S (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
|
No Preview Available !
MITMSUITBSIUSBHISLHSIIsLSIs
M5MM5M444422660C0JC,TJP-,5T,-P6,--75,-,5-S6,-,6-S7,-,7S
-5S,-6S,-7S
FASFTASPTAGPAEGMEOMDOE D4E19441390443-B04IT-B(I2T62(2164241-W44O-WRODRBDY B1Y6-B16IT-B) IDTY) NDAYMNAICMRICAMRAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs,
fabricated with the high performance CMOS process, and is ideal
for memory systems where high speed, low power dissipation, and
low costs are essential.
The use of double-layer metalization process technology and a
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is small enough for
battery back-up application.
This device has 2CAS and 1W terminals with a refresh cycle of
512 cycles every 8.2ms.
FEATURES
Type name
M5M44260CXX-5,-5S
M5M44260CXX-6,-6S
M5M44260CXX-7,-7S
XX=J,TP
RAS
CAS
access access
time time
(max.ns) (max.ns)
50 13
60 15
70 20
Address OE
access access
time time
(max.ns) (max.ns)
25 13
30 15
35 20
Cycle
time
Power
dissipa-
tion
(min.ns) (typ.mW)
90 625
110 550
130 475
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
CMOS Input level
5.5mW (Max)
CMOS Input level
550µW (Max) *
Operating power dissipation
M5M44260Cxx-5,-5S
688mW (Max)
M5M44260Cxx-6,-6S
605mW (Max)
M5M44260Cxx-7,-7S
523mW (Max)
Self refresh capability *
Self refresh current
150µA (Max)
Extended refresh capability
Extended refresh current
150µA (Max)
Fast-page mode (512-column random access), Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, LCAS / UCAS and OE to control output buffer
impedance
512 refresh cycles every 8.2ms (A0~A8)
512 refresh cycles every 128ms (A0~A8) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S
: option) only
APPLICATION
Microcomputer memory, Refresh memory for CRT
PIN DESCRIPTION
Pin name
Function
A0~A8
Address inputs
DQ1~DQ16 Data inputs / outputs
RAS
LCAS
Row address strobe input
Lower byte control
column address strobe input
UCAS
Upper byte control
column address strobe input
W Write control input
OE Output enable input
VCC Power supply (+5V)
VSS Ground (0V)
1 M5M44260CJ,TP-5,-5S : Under development
PIN CONFIGURATION (TOP VIEW)
(5V)VCC 1
DQ1
DQ2
DQ3
2
3
4
DQ4 5
(5V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
NC 12
W 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
(5V)VCC 20
40 VSS(0V)
39 DQ16
38 DQ15
37 DQ14
36 DQ13
35 VSS(0V)
34 DQ12
33 DQ11
32 DQ10
31 DQ9
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS(0V)
Outline 40P0K (400mil SOJ)
(5V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
(5V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
44 VSS(0V)
43 DQ16
42 DQ15
41 DQ14
40 DQ13
39 VSS(0V)
38 DQ12
37 DQ11
36 DQ10
35 DQ9
NC 13
NC 14
W 15
RAS 16
NC 17
A0 18
A1 19
A2 20
A3 21
(5V)VCC 22
32 NC
31 LCAS
30 UCAS
29 OE
28 A8
27 A7
26 A6
25 A5
24 A4
23 VSS(0V)
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC: NO CONNECTION
1 page  
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Fast-Page Mode Cycles)
(Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted, see notes 6,13,14)
Limits
Symbol
Parameter
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Unit
Min Max Min Max Min Max
tREF
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
tT
Refresh cycle time
Refresh cycle time *
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, CAS high to data
Delay time, OE high to data
Transition time
8.2 8.2 8.2
128 128 128
30 40 50
(Note 15) 18
37 20
45 20
50
555
000
10 10 10
(Note 16) 13
25 15
30 15
35
000
(Note 17) 0
7 0 10 0 10
8 10 10
13 15 15
(Note 18) 0 0 0
(Note 18) 0 0 0
(Note 19) 13 15 20
(Note 19) 13 15 20
(Note 20) 1 50 1 50 1 50
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
16: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS RAS low pulse width
tCAS CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read setup time before CAS low
tRCH
Read hold time after CAS high
tRRH
Read hold time after RAS high
tRAL Column address to RAS hold time
tOCH
CAS hold time after OE low
tORH
RAS hold time after OE low
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Limits
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Min Max Min Max Min Max
90 110 130
50 10000 60 10000 70 10000
13 10000 15 10000 20 10000
50 60 70
13 15 20
0 00
(Note 21) 0 0 0
(Note 21) 0 0 0
25 30 35
13 15 20
13 15 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
M5M44260CJ,TP-5,-5S : Under development
5 Page 
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Write Cycle (Early write)
RAS
VIH
VIL
UCAS
(or LCAS)
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
A0~A8
VIH
VIL
VIH
W
VIL
tCRP
tRCD
tWC
tRAS
tCSH
tRSH
tCAS
tASR tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tWCS
tWCH
tRP
tRPC
tCRP
tCPN
tASR
ROW
ADDRESS
DQ1~DQ8 VIH
(or DQ9~DQ16)
(INPUTS) VIL
DQ1~DQ8 VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
DQ9~DQ16 VIH
(or DQ1~DQ8)
(INPUTS) VIL
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
Hi-Z
tDS tDH
DATA VALID
Hi-Z
VIH
OE
VIL
11 M5M44260CJ,TP-5,-5S : Under development
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet M5M44260CTP-6S.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M5M44260CTP-6 | FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM | Mitsubishi |
| M5M44260CTP-6S | FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM | Mitsubishi |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |