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PDF M5K4164AL-12 Data sheet ( Hoja de datos )
| Número de pieza | M5K4164AL-12 | |
| Descripción | 64K-BIT DYNAMIC RAM | |
| Fabricantes | Mitsubishi | |
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MITSUBISHI LSls
M5K4164AL-12, -15
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 65536-word by l-bit dynamic RAMs,
fabricated with the high performance N-channel silicongate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process technology and a single-transistor dynamic storage
cell privide high circuit density at reduced costs, and the
use of dynamic circuitry including sense amplifiers assures
low power dissipation. Multiplexed address inputs permit
both a reduction in pins to the 16-pin zigzag inline package
configuration and an increase in system densities. The
M5K4164AL operates on a 5V power supply using the
on-chip substrate bias generator.
PIN CONFIGURATION (TOP VIEW)
ADDRESS INPUT
COLUMN ADDRESS
STROBE INPUT
REFRESH INPUT
WRITE CONT.ROL
INPUT
ADDRESS
INPUTS
A6 !]
[~ --+ Q
DATA OUTPUT
faCAS --+ ~]
3:
Vss (OV)
REF --+
§]
'" L_
~ [§
<--
0
DATA INPUT
fl ~ [12W --+
Ao
~1
~
".
.L-~
<--
- - ROW ADDRESS
RAS STROBE INPUT
<-- A2 ADDRESS INPUT
A,
--+
lJ]
J">
.!.
IT)1
Vee (5V)
A7 --+ 1}1
A4 --+ l§J
'" [(4 <-- AS} ADDRESS
[(6 <-- A3 INPUTS
FEATURES
• High speed
Type name
MSK4164AL-12
MSK4164AL-15
Access time
(max)
ins)
120
150
Cycle time
{min)
(ns)
220
260
Power dissipalion
(typl
(mWI
175
150
• 16 pin zigzag inline package
• Single 5V±1 0% supply
• Low standby power dissipation: 22mW (max)
• Low operating power dissipation:
M5K4164AL-12 275mW (max)
M5K4164AL-15 250mW (max)
• Unlatched output enables two-dimensional chip selec-
tion a nd extended page boundary
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only refresh, and page-mode
capabilities
Outline 16P5A
• All input terminals have low input capaciatance and are
directly TTL-compatible
• Output is three-state and directly TTL-compatible
• 128 refresh cycles every 2ms
(16K dynamic RAMs M5K4116P, S compatible)
• CAS controlled output allows hidden refresh
• Output data can be held infinitely by CAS
APPLICATION
• Main memory unit for computers
• Refresh memory for CRT
BLOCK DIAGRAM
DATA INPUT
WRITE CONTROL INPUT
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
REFRESH INPUT REF
ADDRESS INPUTS
COLUMN DECODER
MEMORY CELL
164 ROWS X 256 COLUMNS I
SENSE REFRESH AMPLIFIER
MEMORY CELL
164 ROWS X 256 COLUMNSI
COLUMN DECODER
MEMORY CELL
164 ROWS X 256 COLUMNSI
SENSE REFRESH AMPLIFIER
164 ROMWESMXOR2Y56CCEOLLUMNSI
COLUMN DECODER
2 Q DATA OUTPUT
J'
2-34
• MITSUBISHI
"ELECTRIC
1 page  
MITSUBISHI LSls
M5K4164AL·12, ·15
65 536·BI"I' (65 536·WORD BY I.BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(Ta =0 ~70"C. Vcc=5V ± 10%. VSS=OV. unless otherwise noted. See notes 5, 6 and'7)
Symbol
Parameter
IORF
I W(RASH)
IW(RASLJ
I W(CASLJ
I W(CASH)
t h (RAS-CAS)
I h (CAS- RAS)
Id (CAS-RAS)
I d (RAS-CAS)
I su (RA- RAS)
I SU (CA-CAS)
I h (RAS-RA)
I h (CAS-CA)
I h (RAS-CA)
ITHL
I TLH
Refresh cycle time
RAS high pulse width
RAS low purse width
CAS low pulse width
CAS high pulse width
CAS hold time after RAS
RAS hold time a:fter CAS
Delay ti me, CAS to RAS
Delay time, RAS to CAS
Row address setup time before RAS
Column address setup time before CAS
Row address hold time after RA"'S
Column address hold time after CAS
Column address hold time after RAS
Transition time
INoteSI
INote 91
INote 101
Alternative
Symbol
I REF
t RP
I RAS
ICAS
ICPN
ICSH
I RSH
tCRP
I RCO
I ASR
I ASC
I RAH
I CAH
I AR
IT
M5K4164AL-12
Limits
Min Max
2
90
120 10000
60 00
30
120
60
~20
25 60
0
0
15
20
90
3 35
M5K4164AL-15
Limits
Min Max
2
100
150 10000
75 00
35
150
75
-20
30 75
0
0
20
25
95
3 50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 5
6
10'
An initial pause of 500~s is required aft!'!r power·up followed by a.ny eight REF, RAS or RAS/CAS cycles before proper device operation is achieved.
The switching characteristics are defined as t THL = t TLH = 5ns.
Reference levels of input signals are VIH min. and Vil max. Reference levels for transition time are also between VIH and Vil.
Except for page· mode.
td(CAS·RAS) requirement is only applicable for RAS/CA~ cycles preceeded by a CAS only cycle (i.e., For systems where CAS has not been decoded with RAS)
Operation within the td (RAS-CAS) max limit insures that- t a (RAS) max can be· met. td (RAS-CAS)ma x is specified reference point onlY,if
td (RAS-CAS) is greater than the specified td (RAS-CAS) max limit. then access time is controlled exclusively by taICAS).
Id (RAS-CAslmln = Ih (RAS-RA)mln + 21 THL(t TLH) + I su (CA-CAS)mln,
SWITCHING CHARACTERISTICS (Ta=0-70'C, Vcc=5V±10%, VSs=OV, unlessotherwisenoted)
Read Cycle
Symbol
lOR
tsu ,IR-CAS)
Ih (CAS-R)
Ih (RAS-RI
Idls (CAS)
la (CAS)
la (RAS)
Parameter
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after RAS
Output disable time
CAS access time
RAS access time
INote 111
INote 111
INote 121
INote 131
(Note 141
Alternative
Symbol
I RC
t RCS
IRCH
tRRH
IOFF
I CAC
I RAC
M5K4164AL-12
limits
Min Max
220
0
0
10
0 35
60
120
M5K4164AL-15
Limits
Min Max
260
0
0
20
0 40
75
150
Unit
ns
ns
ns
ns
ns
ns
ns
Note 11
Note 12:
Note 13:
Note 14
Either th (RAS-R) or th (CAS-R) must be satisfied for a read cycle,
tdls (CAS)maX defines the time at which the output achieves the open circuit condition and is not reference to VO H or Vo l
This is the value when't9 (RAS-CAS)~td (RAS-CAs)max. Test conditions; Load == 2T TL. Cl == 100pF
This is the value when td (RAS-CAS)< td (RAS-CAS)max. When td (RAS-CAS)~td (RAS-CAS)max. ta (RAS) will incre?se by the amount that
td (RAS-CAS) exceeds the value shown Test conditions; Load == 2T TL. Cl "" 100pF
Write Cycle
Symbol
Parameter
low
Isu (W-CAS)
Ih (CAS-W)
Ih (RAS-W)
Ih (W-RAS)
Ih (W-CAS)
Iw(W)
Isu (O-CAS)
Ih (CAS-D)
Ih (RAS-O)
Write cycle time
Write setup time before CAS
Write hold time after CAS
Write hold time after RAS
RA'S"'hold time after write
CAS hold time after write
Write pulse width
Data·in setup time before CAS
Data·in hold time after CAS
Data·in hold time after RAS
Alternative
Symbol
(NC?te 17)
I RC
IWCS
IWCH'
IWCR
IRWL
ICWL
twp
los
IOH
IOHR
M5K4164AL-12
Limits
Min Max
220
-5
40
90
40
40
40
0
40
90
M5K4164AL-15
Limits
Min Max
260
-5
45
95
45
45
45
0
45
95
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-38
• MITSUBISHI
"'ELECTRIC
5 Page 
MITSUBISHI LSls
M5K4164AL-12, -IS
6SS36·BIT (6S S36·WORD BY 1.BIT)DYNAMIC RAM
Hidden Self-Refresh Cycle
READ CYCLE
W V,H
V,L
REF
V,H
V,L
VOH
Q
VOL
DATA VALID
Note 22. If the pin 5 (REF) function is not used, pin 5 may be left open (not connect).
Hidden Refresh Cycle INote 191
READ CYCLE
leR
REFRESH CYCLE
teR
IW(RASL)
Iw( RASL)
td(CAS-RAS)
Id (RAS-CAS)
tw (RASH)
th (CAS- RAS)
Iwl CASL)
Idls (CAS)
REFRESH CYCLE
leR
t w ( RASL)
Iw (RASH)
Iwl CASH)
IsuIRA-RAS) th(RAS-RA)
Isu (RA-RAS)
ROW
V,H
W
V,L
VOH
Q
VOL
2,--44
DATA VALID
• . MITSUBISHI
"ELECTRIC
tdls (CAS)
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet M5K4164AL-12.PDF ] | |
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