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PDF M59DR008 Data sheet ( Hoja de datos )
| Número de pieza | M59DR008 | |
| Descripción | 8 Mbit 512Kb x16 / Dual Bank / Page Low Voltage Flash Memory | |
| Fabricantes | ST Microelectronics | |
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M59DR008E
M59DR008F
8 Mbit (512Kb x16, Dual Bank, Page) Low Voltage Flash Memory
PRODUCT PREVIEW
s SUPPLY VOLTAGE
– VDD = VDDQ = 1.65V to 2.2V: for Program,
Erase and Read
– VPP = 12V: optional Supply Voltage for fast
Program and Erase
s ASYNCHRONOUS PAGE MODE READ
– Page Width: 4 words
– Page Access: 35ns
– Random Access: 100ns
s PROGRAMMING TIME
– 10µs by Word typical
– Double Word Programming Option
s MEMORY BLOCKS
– Dual Bank Memory Array: 4 Mbit - 4 Mbit
– Parameter Blocks (Top or Bottom location)
– Main Blocks
s DUAL BANK OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
s BLOCK PROTECTION/UNPROTECTION
– All Blocks protected at Power Up
– Any combination of Blocks can be protected
– WP for Block Locking
s COMMON FLASH INTERFACE (CFI)
s 64 bit SECURITY CODE
s ERASE SUSPEND and RESUME MODES
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s 20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M59DR008E: A2h
– Device Code, M59DR008F: A3h
TSOP48 (N)
12 x 20mm
BGA
FBGA48 (ZB)
8 x 6 solder balls
Figure 1. Logic Diagram
VDD VDDQ VPP
19
A0-A18
16
DQ0-DQ15
W
E M59DR008E
G M59DR008F
RP
WP
VSS
AI03212
October 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/37
1 page  
M59DR008E, M59DR008F
Table 7. Bank Size and Sectorization
Bank Size
Bank A
4 Mbit
Bank B
4 Mbit
Parameter Blocks
8 blocks of 4 KWord
-
Main Blocks
7 blocks of 32 KWord
8 blocks of 32 KWord
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A18). The address inputs
for the memory array are latched during a write op-
eration on the falling edge of Chip Enable E or
Write Enable W, whichever occurs last.
Data Input/Output (DQ0-DQ15). The Input is
data to be programmed in the memory array or a
command to be written to the Command Interface
(C.I.) Both input data and commands are latched
on the rising edge of Write Enable W. The Ouput
is data from the Memory Array, the Common Flash
Interface, the Electronic Signature Manufacturer
or Device codes, the Block Protection status, the
Configuration Register status or the Status Regis-
ter Data Polling bit DQ7, the Toggle Bits DQ6 and
DQ2, the Error bit DQ5. The data bus is high im-
pedance when the chip is deselected, Output En-
able G is at VIH, or RP is at VIL.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E at VIH deselects
the memory and reduces the power consumption
to the standby level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at VIL.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is at VIH the outputs are High im-
pedance.
Write Enable (W). This input controls writing to
the Command Register and Data latches. Data are
latched on the rising edge of W.
Write Protect (WP). This input gives an addition-
al hardware protection level against program or
erase when pulled at VIL, as described in the Block
Lock instruction description.
Reset/Power Down Input (RP). The RP input
provides hardware reset of the memory (without
affecting the Configuration Register status), and/
or Power Down functions, depending on the Con-
figuration Register status. Reset/Power Down of
the memory is achieved by pulling RP to VIL for at
least tPLPH. When the reset pulse is given, if the
memory is in Read, Erase Suspend Read or
Standby, it will output new valid data in tPHQ7V1 af-
ter the rising edge of RP. If the memory is in Erase
or Program modes, the operation will be aborted
and the reset recovery will take a maximum ot
tPLQ7V. The memory will recover from Power
Down (when enabled) in tPHQ7V2 after the rising
edge of RP. See Tables 25, 26 and Figure 9.
VDD and VDDQ Supply Voltage (1.65V to 2.2V).
The main power supply for all operations (Read,
Program and Erase). VDD and VDDQ must be at
the same voltage.
VPP Programming Voltage (11.4V to 12.6V). Used
to provide high voltage for fast factory program-
ming. High voltage on VPP pin is required to use
the Double Word Program instruction. It is also
possible to perform word program or erase instruc-
tions with VPP pin grounded.
VSS Ground. VSS is the reference for all the volt-
age measurements.
DEVICE OPERATIONS
The following operations can be performed using
the appropriate bus cycles: Read Array (Random,
and Page Modes), Write command, Output Dis-
able, Standby, Reset/Power Down and Block
Locking. See Table 8.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register, the CFI, the Block
Protection Status or the Configuration Register
status. Read operation of the memory array is per-
formed in asynchronous page mode, that provides
fast access time. Data is internally read and stored
in a page buffer. The page has a size of 4 words
and is addressed by A0-A1 address inputs. Read
operations of the Electronic Signature, the Status
Register, the CFI, the Block Protection Status, the
Configuration Register status and the Security
Code are performed as single asyncronous read
cycles (Random Read). Both Chip Enable E and
Output Enable G must be at VIL in order to read the
output of the memory.
Write. Write operations are used to give Instruc-
tion Commands to the memory or to latch Input
Data to be programmed. A write operation is initi-
ated when Chip Enable E and Write Enable W are
at VIL with Output Enable G at VIH. Addresses are
latched on the falling edge of W or E whichever oc-
curs last. Commands and Input Data are latched
on the rising edge of W or E whichever occurs first.
Noise pulses of less than 5ns typical on E, W and
G signals do not start a write cycle.
5/37
5 Page 
Table 14A. Instructions (1,2)
Mne.
Instr.
Cyc.
RD (4)
Read/Reset
Memory Array
Addr. (3)
1+
Data
Addr.
3+
Data
RCFI CFI Query
Addr.
1+
Data
AS (4) Auto Select
Addr.
3+
Data
CR
Configuration
Register Write
PG Program
Addr.
4
Data
Addr.
4
Data
DPG
Double Word
Program
EBY
Enter Bypass
Mode
XBY
Exit Bypass
Mode
PGBY
Program in
Bypass Mode
Addr.
5
Data
Addr.
3
Data
Addr.
2
Data
Addr.
2
Data
Double Word
DPGBY Program in
Bypass Mode
Addr.
3
Data
BP Block Protect
BU Block Unprotect
Addr.
4
Data
Addr.
1
Data
M59DR008E, M59DR008F
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.
X
Read Memory Array until a new write cycle is initiated.
F0h
555h
AAh
2AAh
55h
555h
F0h
Read Memory Array until a new
write cycle is initiated.
55h
Read CFI data until a new write cycle is initiated.
98h
555h
AAh
2AAh
55h
555h
90h
Read electronic Signature or
Block Protection or Configuration
Register Status until a new cycle
is initiated.
555h
2AAh
555h
Configura-
tion Data
AAh 55h 60h 03h
555h
AAh
2AAh
55h
555h
A0h
Program
Address
Program
Data
Read Data Polling or
Toggle Bit until
Program completes.
555h
AAh
2AAh
55h
555h
40h
Program
Address 1
Program
Data 1
Program
Address 2
Program
Data 2
Note 6, 7
555h
2AAh
555h
AAh 55h 20h
XX
90h 00h
X
Program
Address Read Data Polling or Toggle Bit until Program
A0h
Program completes.
Data
X
Program Program
Address 1 Address 2
40h
Program Program
Data 1 Data 2
Note 6, 7
555h
2AAh
555h
Block
Address
AAh 55h 60h 01h
555h
2AAh
555h
Block
Address
AAh 55h 60h D0h
11/37
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