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PDF M58WR128EB Data sheet ( Hoja de datos )
| Número de pieza | M58WR128EB | |
| Descripción | 128 Mbit 8Mb x 16 / Multiple Bank / Burst 1.8V Supply Flash Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M58WR128ET
M58WR128EB
128 Mbit (8Mb x 16, Multiple Bank, Burst)
1.8V Supply Flash Memory
PRODUCT PREVIEW
FEATURES SUMMARY
s SUPPLY VOLTAGE
– VDD = 1.65V to 2.2V for Program, Erase and
Read
– VDDQ = 1.65V to 3.3V for I/O Buffers
– VPP = 12V for fast Program (optional)
s SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 54MHz
– Asynchronous/ Synchronous Page Read
mode
– Random Access: 70, 80, 100ns
s SYNCHRONOUS BURST READ SUSPEND
s PROGRAMMING TIME
– 8µs by Word typical for Fast Factory Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
s MEMORY BLOCKS
– Multiple Bank Memory Array: 4 Mbit Banks
– Parameter Blocks (Top or Bottom location)
s DUAL OPERATIONS
– Program Erase in one Bank while Read in
others
– No delay between Read and Write operations
s BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WP for Block Lock-Down
s SECURITY
– 128 bit user programmable OTP cells
– 64 bit unique device number
– One parameter block permanently lockable
s COMMON FLASH INTERFACE (CFI)
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
Figure 1. Package
FBGA
VFBGA60 (ZB)
12.5 x 12mm
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M58WR128ET: 881Eh
– Bottom Device Code, M58WR128EB: 881Fh
May 2003
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/87
1 page  
M58WR128ET, M58WR128EB
Figure 17. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 23. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 18. Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 24. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 19. VFBGA60 12.5x12mm - 8x7 ball array, 0.75mm pitch, Bottom View Package Outline . 54
Table 25. VFBGA60 12.5x12mm - 8x7 ball array, 0.75mm pitch, Package Mechanical Data. . . . . 55
Figure 20. VFBGA60 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 56
Figure 21. VFBGA60 Daisy Chain - PCB Connection Proposal (Top view through package) . . . . 57
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 27. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 28. M58WR128ET - Parameter Bank Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 29. M58WR128ET -Main Bank Base Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 30. M58WR128ET - Block Addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 31. M58WR128EB - Parameter Bank Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 32. M58WR128EB - Main Bank Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 33. M58WR128EB - Block Addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 34. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 35. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 36. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 37. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 38. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 39. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 40. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 41. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 42. Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 43. Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 22. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 23. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 24. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 25. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 73
Figure 26. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 27. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 28. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 29. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 77
Figure 30. Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5/87
5 Page 
M58WR128ET, M58WR128EB
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A22). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Bus Write
operation.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable or Write Enable
whichever occurs first.
Write Protect (WP). Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at VIL, the Lock-
Down is enabled and the protection status of the
Locked-Down blocks cannot be changed. When
Write Protect is at VIH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or un-
locked. (refer to Table 13, Lock Status).
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at VIL,
the memory is in reset mode: the outputs are high
impedance and the current consumption is re-
duced to the Reset Supply Current IDD2. Refer to
Table 18, DC Characteristics - Currents for the val-
ue of IDD2. After Reset all blocks are in the Locked
state and the Configuration Register is reset.
When Reset is at VIH, the device is in normal op-
eration. Exiting reset mode the device enters
asynchronous read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to VRPH
(refer to Table 19, DC Characteristics).
Latch Enable (L). Latch Enable latches the ad-
dress bits on its rising edge. The address
latch is transparent when Latch Enable is at
VIL and it is inhibited when Latch Enable is at
VIH. Latch Enable can be kept Low (also at
board level) when the Latch Enable function
is not required or supported.
Clock (K). The clock input synchronizes the
memory to the microcontroller during synchronous
read operations; the address is latched on a Clock
edge (rising or falling, according to the configura-
tion settings) when Latch Enable is at VIL. Clock is
don't care during asynchronous read and in write
operations.
Wait (WAIT). Wait is an output signal used during
synchronous read to indicate whether the data on
the output bus are valid. This output is high imped-
ance when Chip Enable is at VIH or Reset is at VIL.
It can be configured to be active during the wait cy-
cle or one clock cycle in advance. The WAIT signal
is not gated by Output Enable.
VDD Supply Voltage . VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from VDD. VDDQ can be
tied to VDD or can use a separate supply.
VPP Program Supply Voltage. VPP is both a
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin.
If VPP is kept in a low voltage range (0V to VDDQ)
VPP is seen as a control input. In this case a volt-
age lower than VPPLK gives an absolute protection
against program or erase, while VPP > VPP1 en-
ables these functions (see Tables 18 and 19, DC
Characteristics for the relevant values). VPP is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase op-
erations continue.
If VPP is in the range of VPPH it acts as a power
supply pin. In this condition VPP must be stable un-
til the Program/Erase algorithm is completed.
VSS Ground. VSS ground is the reference for the
core supply. It must be connected to the system
ground.
VSSQ Ground. VSSQ ground is the reference for
the input/output circuitry driven by VDDQ. VSSQ
must be connected to VSS
Note: Each device in a system should have
VDD, VDDQ and VPP decoupled with a 0.1µF ce-
ramic capacitor close to the pin (high frequen-
cy, inherently low inductance capacitors
should be as close as possible to the pack-
11/87
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M58WR128EB.PDF ] | |
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