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PDF M58MR032C Data sheet ( Hoja de datos )

Número de pieza M58MR032C
Descripción 32 Mbit 2Mb x16 / Mux I/O / Dual Bank / Burst 1.8V Supply Flash Memory
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M58MR032C
M58MR032D
32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst)
1.8V Supply Flash Memory
PRELIMINARY DATA
s SUPPLY VOLTAGE
– VDD = VDDQ = 1.7V to 2.0V for Program,
Erase and Read
– VPP = 12V for fast Program (optional)
s MULTIPLEXED ADDRESS/DATA
s SYNCHRONOUS / ASYNCHRONOUS READ
– Burst mode Read: 40MHz
– Page mode Read (4 Words Page)
– Random Access: 100ns
s PROGRAMMING TIME
– 10µs by Word typical
– Two or four words programming option
s MEMORY BLOCKS
– Dual Bank Memory Array: 8/24 Mbit
– Parameter Blocks (Top or Bottom location)
s DUAL OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
s PROTECTION/SECURITY
– All Blocks protected at Power-up
– Any combination of Blocks can be protected
– 64 bit unique device identifier
– 64 bit user programmable OTP cells
– One parameter block permanently lockable
s COMMON FLASH INTERFACE (CFI)
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M58MR032C: 88DAh
– Bottom Device Code, M58MR032D: 88DBh
FBGA
TFBGA48 (ZC)
10 x 4 ball array
Figure 1. Logic Diagram
VDD VDDQ VPP
5
A16-A20
16
ADQ0-ADQ15
W
E WAIT
G M58MR032C
M58MR032D
RP BINV
WP
L
K
VSS
AI90019
August 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/52

1 page




M58MR032C pdf
M58MR032C, M58MR032D
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs or Data Input/Output (ADQ0-
ADQ15). When Chip Enable E is at VIL and Out-
put Enable G is at VIH the multiplexed address/
data bus is used to input addresses for the memo-
ry array, data to be programmed in the memory ar-
ray or commands to be written to the C.I. The
address inputs for the memory array are latched
on the rising edge of Latch Enable L. The address
latch is transparent when L is at VIL. In synchro-
nous operations the address is also latched on the
first rising/falling edge of K (depending on clock
configuration) when L is low. Both input data and
commands are latched on the rising edge of Write
Enable W. When Chip Enable E and Output En-
able G are at VIL the address/data bus outputs
data from the Memory Array, the Electronic Signa-
ture Manufacturer or Device codes, the Block Pro-
tection status the Read Configuration Register
status, the protection register or the Status Regis-
ter. The address/data bus is high impedance when
the chip is deselected, Output Enable G is at VIH,
or RP is at VIL.
Address Inputs (A16-A20). The five MSB ad-
dresses of the memory array are latched on the
rising edge of Latch Enable L. In synchronous op-
eration these inputs are also latched on the first
rising/falling edge of K (depending on clock config-
uration) when L is low.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E at VIH deselects
the memory and reduces the power consumption
to the standby level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at VIL.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is at VIH the outputs are High im-
pedance.
Write Enable (W). This input controls writing to
the Command Register and Data latches. Data are
latched on the rising edge of W.
Write Protect (WP). This input gives an addition-
al hardware protection level against program or
erase when pulled at VIL, as described in the Block
Lock instruction description.
Reset/Power-down Input (RP). The RP input
provides hardware reset of the memory, and/or
Power-down functions, depending on the Read
Configuration Register status. Reset/Power-down
of the memory is achieved by pulling RP to VIL for
at least tPLPH. When the reset pulse is given, the
memory will recover from Power-down (when en-
abled) in a minimum of tPHEL, tPHLL or tPHWL (see
Table 31 and Figure 15) after the rising edge of
RP. Exit from Reset/Power-down changes the
contents of the Read Configuration Register bits
14 and 15, setting the memory in asynchronous
page mode read and power save function dis-
abled. All blocks are protected and unlocked after
a Reset/Power-down.
Latch Enable (L). L latches the address bits
ADQ0-ADQ15 and A16-A20 on its rising edge.
The address latch is transparent when L is at VIL
and it is inhibited when L is at VIH.
Clock (K). The clock input synchronizes the
memory to the micro controller during burst mode
read operation; the address is latched on a K edge
(rising or falling, according to the configuration set-
tings) when L is at VIL. K is don’t care during asyn-
chronous page mode read and in write operations.
Wait (WAIT). WAIT is an output signal used dur-
ing burst mode read, indicating whether the data
on the output bus are valid or a wait state must be
inserted. This output is high impedance when E or
G are high or RP is at VIL, and can be configured
to be active during the wait cycle or one clock cy-
cle in advance.
Bus Invert (BINV). BINV is an input/output signal
used to reduce the amount of power needed to
switch the external address/data bus. The power
saving is achieved by inverting the data output on
ADQ0-ADQ15 every time this gives an advantage
in terms of number of toggling bits. In burst mode
read, each new data output from the memory is
compared with the previous data. If the number of
transitions required on the data bus is in excess of
8, the data is inverted and the BINV signal will be
driven by the memory at VOH to inform the receiv-
ing system that data must be inverted before any
further processing. By doing so, the actual transi-
tions on the data bus will be less than 8.
In a similar way, when a command is given, BINV
may be driven by the system at VIH to inform the
memory that the data input must be inverted.
Like the other input/output pins, BINV is high im-
pedance when the chip is deselected, output en-
able G is at VIH or RP is at VIL; when used as an
input, BINV must follow the same set-up and hold
timings of the data inputs.
VDD and VDDQ Supply Voltage (1.7V to 2.0V).
VDD is the main power supply for all operations
(Read, Program and Erase). VDDQ is the supply
voltage for Input and Output.
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M58MR032C arduino
M58MR032C, M58MR032D
INSTRUCTIONS AND COMMANDS
Eighteen instructions are available (see Tables 10
and 11) to perform Read Memory Array, Read Sta-
tus Register, Read Electronic Signature, CFI Que-
ry, Block Erase, Bank Erase, Program, Tetra Word
Program, Double Word Program, Clear Status
Register, Program/Erase Suspend, Program/
Erase Resume, Block Protect, Block Unprotect,
Block Lock, Protection Register Program, Read
Configuration Register and Lock Protection Pro-
gram.
Status Register output may be read at any time,
during programming or erase, to monitor the
progress of the operation.
An internal Command Interface (C.I.) decodes the
instructions while an internal Program/Erase Con-
troller (P/E.C.) handles all timing and verifies the
correct execution of the Program and Erase in-
structions. P/E.C. provides a Status Register
whose bits indicate operation and exit status of the
internal algorithms. The Command Interface is re-
set to Read Array when power is first applied,
when exiting from Reset or whenever VDD is lower
than VLKO. Command sequence must be followed
exactly. Any invalid combination of commands will
reset the device to Read Array.
Read (RD)
The Read instruction consists of one write cycle
(refer to Device Operations section) and places
the addressed bank in Read Array mode. When a
device reset occurs, the memory is in Read Array
as default. A read array command will be ignored
while a bank is programming or erasing. However
in the other bank a read array command will be ac-
cepted.
Read Status Register (RSR)
A bank’s Status Register indicates when a pro-
gram or erase operation is complete and the suc-
cess or failure of operation itself. Issue a Read
Status Register Instruction (70h) to read the Sta-
tus Register content of the addressed bank. The
status of the other bank is not affected by the com-
mand. The Read Status Register instruction may
be issued at any time, also when a Program/Erase
operation is ongoing. The following Read opera-
tions output the content of the Status Register of
the addressed bank. The Status Register is
latched on the falling edge of E or G signals, and
can be read until E or G returns to VIH. Either E or
G must be toggled to update the latched data.
Read Electronic Signature (RSIG)
The Read Electronic Signature instruction con-
sists of one write cycle (refer to Device Operations
section) giving the command 90h to an address
Table 10. Commands
Hex Code
Command
00h Invalid Reset
01h Protect Confirm
03h
Write Read Configuration Register
Confirm
10h Alternative Program Set-up
20h Block Erase Set-up
2Fh Lock Confirm
30h Double Word Program Set-up
40h Program Set-up
50h Clear Status Register
55h Tetra Word Program Set-up
60h
Protect Set-up and Write Read
Configuration Register
70h Read Status Register
80h Bank Erase Set-up
90h Read Electronic Signature
98h CFI Query
B0h Program/Erase Suspend
C0h
Protection Program and Lock Protection
Program
D0h
Program/Erase Resume, Erase Confirm
or Unprotect Confirm
FFh Read Array
within the bank A. A subsequent read in the ad-
dress of bank A will output the Manufacturer Code,
the Device Code, the protection Status of Blocks
of bank A, the Die Revision Code, the Protection
Register, or the Read Configuration Register (see
Table 9).
If the first write cycle of Read Electronic Signature
instruction is issued to an address within the bank
B, a subsequent read in an address of bank B will
output the protection Status of Blocks of bank B.
The status of the other bank is not affected by the
command (see Table 8).
See Tables 5, 6, 7 and 8 for the valid address. The
Electronic Signature can be read from the memory
allowing programming equipment or applications
to automatically match their interface to the char-
acteristics of M58MR032C and M58MR032D.
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