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PDF M58CR064C10ZB6T Data sheet ( Hoja de datos )

Número de pieza M58CR064C10ZB6T
Descripción 64 Mbit 4Mb x 16 / Dual Bank / Burst 1.8V Supply Flash Memory
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M58CR064C10ZB6T Hoja de datos, Descripción, Manual

M58CR064C, M58CR064D
M58CR064P, M58CR064Q
64 Mbit (4Mb x 16, Dual Bank, Burst )
1.8V Supply Flash Memory
FEATURES SUMMARY
s SUPPLY VOLTAGE
– VDD = 1.65V to 2V for Program, Erase and
Read
– VDDQ = 1.65V to 3.3V for I/O Buffers
– VPP = 12V for fast Program (optional)
s SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode : 54MHz
– Asynchronous/ Synchronous Page Read
mode
– Random Access: 85, 90, 100, 120ns
s PROGRAMMING TIME
– 10µs by Word typical
– Double/Quadruple Word Program option
s MEMORY BLOCKS
– Dual Bank Memory Array: 16/48 Mbit
– Parameter Blocks (Top or Bottom location)
s DUAL OPERATIONS
– Program Erase in one Bank while Read in
other
– No delay between Read and Write operations
s BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WP for Block Lock-Down
s SECURITY
– 128 bit user programmable OTP cells
– 64 bit unique device number
– One parameter block permanently lockable
s COMMON FLASH INTERFACE (CFI)
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
Figure 1. Package
FBGA
TFBGA56 (ZB)
6.5 x 10mm
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M58CR064C: 88CAh
– Bottom Device Code, M58CR064D: 88CBh
– Top Device Code, M58CR064P: 8801h
– Bottom Device Code, M58CR064Q: 8802h
June 2003
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M58CR064C10ZB6T pdf
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 27. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28. Top Boot Block Addresses, M58CR064C, M58CR064P . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 29. Bottom Boot Block Addresses, M58CR064D, M58CR064Q . . . . . . . . . . . . . . . . . . . . . . 52
APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 31. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 33. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 35. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 20. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 21. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 22. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 23. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 61
Figure 24. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 25. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 26. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 65
APPENDIX D. COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 36. Command Interface States - Lock table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 37. Command Interface States - Modify Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 38. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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M58CR064C10ZB6T arduino
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Note: Each device in a system should have
VDD, VDDQ and VPP decoupled with a 0.1µF ce-
ramic capacitor close to the pin (high frequen-
cy, inherently low inductance capacitors
should be as close as possible to the pack-
age). See Figure 9, AC Measurement Load Cir-
cuit. The PCB track widths should be sufficient
to carry the required VPP program and erase
currents.
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Ad-
dress Latch, Output Disable, Standby and Reset.
See Table 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register and the
Common Flash Interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a
read operation. The Chip Enable input should be
used to enable the device. Output Enable should
be used to gate data onto the output. The data
read depends on the previous command written to
the memory (see Command Interface section).
Refer to the Read AC Waveform figures and Char-
acteristics tables in the DC and AC Parameters
section for details of when the output becomes val-
id.
Bus Write. Bus Write operations write Com-
mands to the memory or latch Input Data to be
programmed. A bus write operation is initiated
when Chip Enable and Write Enable are at VIL with
Output Enable at VIH. Commands, Input Data and
Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The
addresses can also be latched prior to the write
operation by toggling Latch Enable. In this case
the Latch Enable should be tied to VIH during the
bus write operation.
See Figures 14 and 15, Write AC Waveforms, and
Tables 22 and 23, Write AC Characteristics, for
details of the timing requirements.
Address Latch. Address latch operations input
valid addresses. Both Chip enable and Latch En-
able must be at VIL during address latch opera-
tions. The addresses are latched on the rising
edge of Latch Enable.
Output Disable. The outputs are high imped-
ance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable and Reset/Power-Down are at
VIH. The power consumption is reduced to the
stand-by level and the outputs are set to high im-
pedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
VIH during a program or erase operation, the de-
vice enters Standby mode when finished.
Reset. During Reset mode the memory is dese-
lected and the outputs are high impedance. The
memory is in Reset mode when Reset/Power-
Down is at VIL. The power consumption is reduced
to the Standby level, independently from the Chip
Enable, Output Enable or Write Enable inputs. If
Reset is pulled to VSS during a Program or Erase,
this operation is aborted and the memory content
is no longer valid.
Table 3. Bus Operations
Operation
E GW L
Bus Read
VIL VIL VIH VIL(2)
Bus Write
VIL VIH VIL VIL(2)
Address Latch
VIL X VIH VIL
Output Disable
VIL VIH VIH
X
Standby
VIH X X X
Reset
XXX X
Note: 1. X = Don’t care.
2. L can be tied to VIH if the valid address has been previously latched.
3. Depends on G.
RP WAIT
DQ15-DQ0
VIH Data Output
VIH Hi-Z
Data Input
VIH Data Output or Hi-Z (3)
VIH Hi-Z
Hi-Z
VIH Hi-Z
Hi-Z
VIL Hi-Z
Hi-Z
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