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PDF M58657P Data sheet ( Hoja de datos )

Número de pieza M58657P
Descripción 1400-BIT(100-WORD BY 14-BIT) ELECTRICALLY ALTERABLE ROM
Fabricantes Mitsubishi 
Logotipo Mitsubishi Logotipo



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MITSUBISHI LSls
M58657P
- -l400-BIT (lOO-WORD BY l4-BIT) ELECTRICALLY ALTERABLE ROM
DESCRIPTION
The M58657P is a serial input/output 1400 bit electrically
erasable and reprogrammable ROM organized as 100 words
of 14 bits, and fabricated using MNOS technology. Data
and addresses are transferred serially via a one-bit bidirec-
tional bus.
FEATURES
• Word-by-word electrically alterable
• Non-volatile data storage . . . . . . . . . . 10 years (min)
• Write/erase time ..... _.......... 20ms word
• Typical power supply voltages ....... -30V, +5V
• Number of erase-write cycles ....... 105 times (min)
• Number of read access unrefreshed ... 109 times (min)
• 5V I/O interface
PIN CONFIGURATION (TOP VIEW)
(5V) Vss
(-30V) VeG
NC
(OV)VGND
NC
CLOCK INPUT CLK ~
MODE CONTROL C,~
INPUT
VMINC)
NC
OATA INPUT!
OUTPUT
NC
NC
~C3
~Cz
} MODE CONTROL
INPUTS
APPLICATION
• Non-volatile channel memories for electronic tuning
systems and field-reprogrammable read-only memory
systems
Outline 14P4
NC NO CONNECTION
FUNCTION
The address is designated by two consecutive one-of-ten-
coded digits. Seven modes-accept address, accept data,
shift data output, erase, write, read, and standby-are
all selected by a 3-bit code applied to C" C2 , and C3 . Data
is stored by internal negative writing pulses that selec-
tively tunnel charges into the Si02-Si3N. interface of the
gate insulators of the MNOS memory transistors.
BLOCK DIAGRAM
1--
coo-
'ooaw":
:i:
to
I
----_.-
1 Vss(SV)
2 VGaI - 30V)
7Cl}
8 Cz MODE CONTROL INPUTS
9 C3
6 CLK CLOCK INPUT
•. MITSUBISHI
..... ELECTRIC
7-9

1 page




M58657P pdf
MITSUBISHI LSls
MS8657P
l400-BIT (100-WORD BY l4-BIT) ELECTRICALLY ALTERABLE ROM
• The difinition of clock duty cycle, D (</»
III
I~ T(L)
IE T(¢)
:1
D(0)=T(U/ T (¢)
• Timing of data input and mode control inputs
Mode control inputs, C1 , C2 , C3 and input signal my
change, when clock is 'H' level.
CLOCK
CMAY
CONTROL LINES
_ _- - J " : -C_HAN_GE - ' ' : -_S_TABL_E _ _- '
INPUT
(ADDRESS/DATA)
ADDRESS DR DATA
STABLE
• Timing of data output
CLOCK
C,
C2
C3
DATA
(OUTPUT)
H
n
\~
The 1st bit of output data is output after access time of
talC) from the mode control transition. And other bits are
output after talC) from positive edge of clock.
tdv
• MITSUBISHI
..... ELECTRIC
7-13

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