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PDF M54HCT574F1R Data sheet ( Hoja de datos )
| Número de pieza | M54HCT574F1R | |
| Descripción | OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT564 INVERTING - HCT574 NON INVERTING | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M54/74HCT564
M54/74HCT574
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT
HCT564 INVERTING - HCT574 NON INVERTING
. HIGH SPEED
fMAX = 62 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.) VIL = 0.8V (MAX)
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH= 6 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS564/574
DESCRIPTION
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCTXXXF1R M74HCTXXXM1R
M74HCTXXXB1R M74HCTXXXC1R
The M54/74HCT564 and M54HCT574 are high
speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-
STATE OUTPUTS fabricated in silicon gate C2MOS
technology. They have the same high speed per-
formance of LSTTL combined with true CMOS low
power comsuption. These 8-bit D-type flip-flops are
controlled by a clock input (CK) and an ouput enable
input (OE). On the positive transition of the clock, the
Q outputs will be set to the logic state that were setup
at the D inputs (HCT574) or their complements
(HCT564).
While the OE input is low, the eight outputs will be
in a normal logic state (high or low logic level), and
while high level, the outputs will be in a high imped-
ance state. The output control does not affect the in-
ternal operation of flip-flops. That is, the old data can
be retained or the new data can be entered even
while the outputs are off. The application engineer
has a choice of combination of inverting and non-in-
verting outputs. The 3-state output configuration
and the wide choice of outline make bus-organized
systems simple. All inputs are equipped with protec-
tion circuits against static discharge and transient
excess voltage. This integrated circuit has input and
output characteristics that are fully compatible with
54/74 LSTTL logic families. M54/74HCT devices
are designed to directly interface HSC2MOS sys-
tems with TTL and NMOS components. They are
also plug in replacements for LSTTL devices giving
a reduction of power consumption.
PIN CONNECTION (top view)
HCT564
HCT574
HCT564
HCT574
September 1993
1/13
1 page  
M54/M74HCT564/574
DC SPECIFICATIONS
Symbol
Parameter
VIH High Level Input
Voltage
VIL Low Level Input
Voltage
VOH High Level
Output Voltage
VOL Low Level Output
Voltage
II Input Leakage
Current
ICC Quiescent Supply
Current
∆ICC Additional worst
case supply
current
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
4.5 2.0 2.0 2.0
to
5.5
4.5 0.8 0.8 0.8
to
5.5
VI = IO=-20 µA 4.4
4.5
VIH
or IO=-6.0 mA 4.18
VIL
4.5
4.31
4.4
4.13
4.4
4.10
VI = IO= 20 µA
4.5
VIH
or IO= 6.0 mA
VIL
0.0 0.1
0.17 0.26
0.1
0.33
0.1
0.4
5.5 VI = VCC or GND
±0.1 ±1
±1
5.5 VI = VCC or GND
4 40 80
5.5 Per Input pin
VI = 0.5V or
VI = 2.4V
Other Inputs at
VCC or GND
IO= 0
2.0 2.9 3.0
Unit
V
V
V
V
µA
µA
mA
5/13
5 Page 
DIM.
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
L
M
S
MIN.
0.10
0.35
0.23
12.60
10.00
7.40
0.50
M54/M74HCT564/574
SO20 MECHANICAL DATA
mm
TYP.
0.50
1.27
11.43
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
0.004
0.013
0.009
45° (typ.)
13.00
0.496
10.65
0.393
7.60 0.291
1.27 0.19
0.75
8° (max.)
inch
TYP.
0.020
0.050
0.450
MAX.
0.104
0.007
0.096
0.019
0.012
0.512
0.419
0.299
0.050
0.029
P013L
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet M54HCT574F1R.PDF ] | |
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