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PDF M54HCT174 Data sheet ( Hoja de datos )
| Número de pieza | M54HCT174 | |
| Descripción | HEX D-TYPE FLIP FLOP WITH CLEAR | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M54HCT174
M74HCT174
HEX D-TYPE FLIP FLOP WITH CLEAR
. HIGH SPEED
fMAX = 56 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.) VIL = 0.8V (MAX)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS174
B1R
(Plastic Package)
M 1R
(Micro Package)
F1R
(Ceramic Package)
C1R
(Chip Carrier)
DESCRIPTION
The M54/74HCT174 is a high speed CMOS HEX D-
TYPE FLIP-FLOP WITH CLEAR fabricated in silicon
gate C2MOS technology. It has the same high speed
performance of LSTTL combined with true CMOS
low power consumption.
Information signals applied to D inputs are transfered
to the Q output on thepositive going edge of the clock
pulse. When the CLEAR input is held low, the Q out-
puts are held low independently of the other inputs.
This integrated circuit has input and output charac-
teristics that are fully compatible with 54/74 LSTTL
logic families. M54/74HCT devices are designed to
directly interface HSC2MOS systems with TTL and
NMOS components. They are also plug in replace-
ments for LSTTL devices giving a reduction of power
consumption. All inputs are equipped with protection
circuits against static discharge and transient excess
voltage.
ORDER CODES :
M54HCT174F1R M74HCT174M1R
M74HCT174B1R M74HCT174C1R
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
February 1993
NC =
No Internal
Connection
1/11
1 page  
M54/M74HCT174
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 4.5
tTHL Time
tPLH Propagation
tPHL Delay Time
(CK - Q)
4.5
8 15 19 22 ns
18 28
35
ns
tPHL Propagation
Delay Time
(CLR - Q)
4.5
18 28 35 42
ns
fMAX Maximum Clock 4.5
Frequency
30 54
24
MHz
tW(H)
tW(L)
Minimum Pulse
Width
(CLOCK)
4.5
8 15 19 22
ns
tW(L) Minimum Pulse
Width
(CLR)
4.5
8 15 19 22
ns
ts Minimum Set-up 4.5
Time
2 10 13 15 ns
th Minimum Hold 4.5
Time
5 6 8 ns
tREM Minimum
Removal Time
4.5
5 5 5 5 ns
CIN Input Capacitance
5 10 10 10 pF
CPD (*) Power Dissipation
Capacitance
68
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC/6 (per FLIP/FLOP)
And the total CPD when N pcs of FLIP FLOP operate can be gained by the following equation: CPD (total)= 38 + 15 x n
5/11
5 Page 
M54/M74HCT174
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
11/11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet M54HCT174.PDF ] | |
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