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PDF M54HCT165F1R Data sheet ( Hoja de datos )

Número de pieza M54HCT165F1R
Descripción 8 BIT PISO SHIFT REGISTER
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M54HCT165F1R Hoja de datos, Descripción, Manual

M54HCT165
M74HCT165
. HIGH SPEED
tPD = 17 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH= 4 mA (MIN.)
. COMPATIBLE WITH TTL OUTPUTS
VIH = 2 V (MIN.) VIL = 0.8 V (MAX.)
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS165
DESCRIPTION
The M54/74HCT165 is a high speed CMOS 8 BIT
PISO SHIFT REGISTER fabricated in silicon gate
C2MOS technology. It has the same high speed
performance of LSTTL combined with true CMOS
low power consumption. It achives the high speed
operation similar to equivalent LSTTL while
maintaining the CMOS low power dissipation.
This device contains eight clocked master slave RS
flip-flops connected as a shift register, with auxiliary
gating to provide over-riding asynchronous parallel
entry. Parallel data entrens when the shift/load input
is low. The parallel data can change while shift/load
is low, provided that the recommended set-up and
hold times are observed. For clocked operation,
shift/load must be high. The two clock input perform
identically; one can be used as a clock inhibit by
applying a high signal; to permit this operation
clocking is accomplished through a 2 input nor
gates.
To avoid double clocking, however, the inhibit signal
should only go high while the clock is high.
Otherwise the rising inhibit signal will cause the
same response as rising clock edge.This integrated
circuit has input and output characteristics that are
fully compatible with 54/74 LSTTL logic families.
M54/74HCT devices are designed to directly
interface HSCMOS systems with TTL and NMOS
components. They are also plug in replacements for
LSTTL devices giving a reduction of power
consumption. All inputs are equipped with
protection circuits against static discharge and
transient excess voltage.
October 1993
8 BIT PISO SHIFT REGISTER
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCT165F1R M74HCT165M1R
M74HCT165B1R M74HCT165C1R
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
1/13

1 page




M54HCT165F1R pdf
M54/M74HCT165
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 4.5
tTHL Time
tPLH Propagation
tPHL Delay Time
(CK - QH, QH)
4.5
8 15 19 22 ns
24 37 46 56 ns
tPLH Propagation
4.5
tPHL Delay Time
(CKINH - QH, QH)
24 37 46 56 ns
tPLH Propagation
tPHL Delay Time
(S/L - QH, QH)
4.5
26 40 50 60 ns
tPLH Propagation
tPHL Delay Time
(H - QH, QH)
4.5
22 34 43 51 ns
fMAX Maximum Clock 4.5
Frequency
30 46
24
MHz
tW(H)
tW(L)
Minimum Pulse
Width
(CK, CKINH)
4.5
8 15 19 22 ns
tW(H)
tW(L)
Minimum Pulse
Width
(S/L)
4.5
8 15
19
ns
ts Minimum Set-up 4.5
Time
(PI - S/L)
7 15 19 22 ns
ts Minimum Set-up 4.5
Time
(S/L -CK, CHINH)
7 15 19 22 ns
ts Minimum Set-up 4.5
Time
(S -CK, CHINH)
7 15 19 22 ns
th Minimum Hold 4.5
Time
(PI - S/L)
(S/L -CK, CHINH)
0 0 0 ns
tREM Minimum
Removal Time
(CK - CKINH)
(CKINH - CK)
4.5
5 15 19 22 ns
CIN
CPD (*)
Input Capacitance
Power Dissipation
Capacitance
5 10 10 10 pF
96 pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC
5/13

5 Page





M54HCT165F1R arduino
DIM.
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
G
L
M
S
M54/M74HCT165
SO16 (Narrow) MECHANICAL DATA
MIN.
0.1
0.35
0.19
9.8
5.8
3.8
4.6
0.5
mm
TYP.
0.5
1.27
8.89
MAX.
1.75
0.2
1.65
0.46
0.25
MIN.
0.004
0.013
0.007
45° (typ.)
10 0.385
6.2 0.228
4.0 0.149
5.3 0.181
1.27 0.019
0.62
8° (max.)
inch
TYP.
0.019
0.050
0.350
MAX.
0.068
0.007
0.064
0.018
0.010
0.393
0.244
0.157
0.208
0.050
0.024
P013H
11/13

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