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Número de pieza | M54HC77 | |
Descripción | 4-BIT D-TYPE LATCH | |
Fabricantes | ST Microelectronics | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de M54HC77 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
No Preview Available ! . HIGH SPEED
tPD = 10 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 2 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS77
DESCRIPTION
The M54/74HC77 is a high speed CMOS 4-BIT D-
TYPE LATCH fabricated in silicon gate C2MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. It contains two groups of 2-bit latches con-
trolled by an enable input (G1 • 2 or G3 • 4). These
two latch groups can be used in different circuits. The
data applied to the data inputs (1D, 2D, or 3D, 4D) are
transfered to the Q outputs (1Q, 2Q, or 3Q, 4Q) re-
spectively when the enable input (G1 • 2 or G3 • 4) is
taken high. The Q outputs will follow the data inputs
as long as the enable input is kept high. When the en-
able input is taken low, the information data applied to
the data inputs is retained at the Q outputs. All inputs
are equipped with protection circuits against static dis-
charge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
M54HC77
M74HC77
4-BIT D-TYPE LATCH
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC77F1R
M 74H C7 7M 1R
M 74HC 77 B1 R
M 74H C7 7C 1R
PIN CONNECTIONS (top view)
October 1992
NC =
No Internal
Connection
1/10
1 page M54/M74HC77
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 2.0
tTHL Time
4.5
30 75
8 15
95 110
19 22 ns
6.0 7 13 16 19
tPLH Propagation
tPHL Delay Time
(DATA - Q)
2.0
4.5
6.0
39 100 125 150
13 20 25 30 ns
11 17 21 26
tPLH Propagation
tPHL Delay Time
(G - Q)
2.0
4.5
6.0
39 100 125 150
13 20 25 30 ns
11 17 21 26
tW(H)
Minimum Pulse
Width
(G)
2.0
4.5
6.0
15 75
6 15
6 13
95 110
19 22 ns
16 19
ts Minimum Set-up 2.0
Time
4.5
15 50 65 75
3 10 13 15 ns
6.0
39
11 13
th Minimum Hold 2.0
Time
4.5
25 30 40
5 6 8 ns
6.0 4 5 7
CIN Input Capacitance
5 10 10 10 pF
CPD (*) Power Dissipation
Capacitance
20
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC/4 (per FLIP/FLOP)
SWITCHING CHARACTERISTICS TEST
WAVEFORM
TEST CIRCUIT ICC (Opr)
INPUTWAVEFORMIS THESAVE AS THAT INCASE OFSWITCH-
ING CHARACTERISTICS TEST.
5/10
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet M54HC77.PDF ] |
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M54HC7240C1R | OCTAL BUS BUFFER WITH 3 STATE OUTPUTS HC7240: INVERTED - HC7241/7244 NON INVERTED | ST Microelectronics |
M54HC7240F1R | OCTAL BUS BUFFER WITH 3 STATE OUTPUTS HC7240: INVERTED - HC7241/7244 NON INVERTED | ST Microelectronics |
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