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PDF M54HC76 Data sheet ( Hoja de datos )

Número de pieza M54HC76
Descripción DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M54HC76
M74HC76
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
. HIGH SPEED
fMAX = 65 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 2 µA (MAX.) AT 25 °C
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH= IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS76
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC76F1R
M 74H C7 6M 1R
M 74HC 76 B1 R
M 74H C7 6C 1R
DESCRIPTION
The M54/74HC76 is a high speed CMOS DUAL J-K
FLIP FLOP fabricated in silicon gate C2MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. Depending on with the logic level at the J
and K inputs this device changes state on the nega-
tive going transition of the clock pulse. CLEAR and
PRESET are independent of the clock and are ac-
complished by a logic low on the corresponding
input. All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
October 1992
NC =
No Internal
Connection
1/11

1 page




M54HC76 pdf
M54/M74HC76
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 2.0
tTHL Time
4.5
30 75
8 15
95 110
19 22 ns
6.0 7 13 16 19
tPLH Propagation
tPHL Delay Time
(CK - Q, Q)
2.0
4.5
6.0
60 125 155 190
15 25 31 38 ns
13 21 26 32
tPLH Propagation
2.0
tPHL Delay Time
4.5
(CLR, PR - Q, Q) 6.0
76 140 175 210
18 28 35 42 ns
16 24 30 36
fMAX Maximum Clock 2.0
Frequency
4.5
6.2 21
31 63
5.0 4.2
25 21 MHz
6.0 37 67 30 25
tW(H)
tW(L)
Minimum Pulse
Width
(CLOCK)
2.0
4.5
6.0
18 75
6 15
6 13
95 110
19 22 ns
16 19
tW(L) Minimum Pulse
Width
(CLR, PR)
2.0
4.5
6.0
22 75
6 15
6 13
95 110
19 22 ns
16 19
ts Minimum Set-up 2.0
Time
4.5
25 75
7 15
95 110
19 22 ns
6.0 6 13 16 19
th Minimum Hold 2.0
Time
4.5
000
0 0 0 ns
6.0 0 0 0
tREM Minimum
Removal Time
(CLR, PR)
2.0
4.5
6.0
20 75
6 15
5 13
95 110
19 22 ns
16 19
CIN Input Capacitance
5 10 10 10 pF
CPD (*) Power Dissipation
Capacitance
38
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC/2 (per FLIP/FLOP)
5/11

5 Page





M54HC76 arduino
M54/M74HC76
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
11/11

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