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PDF M29W160ET Data sheet ( Hoja de datos )

Número de pieza M29W160ET
Descripción 16 Mbit (2Mb x8 or 1Mb x16 / Boot Block) 3V Supply Flash Memory
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M29W160ET
M29W160EB
16 Mbit (2Mb x8 or 1Mb x16, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY
SUPPLY VOLTAGE
– VCC = 2.7V to 3.6V for Program, Erase
and Read
ACCESS TIMES: 70, 90ns
PROGRAMMING TIME
– 10µs per Byte/Word typical
35 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 32 Main Blocks
PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program
algorithms
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
TEMPORARY BLOCK UNPROTECTION
MODE
COMMON FLASH INTERFACE
– 64 bit Security Code
LOW POWER CONSUMPTION
– Standby and Automatic Standby
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29W160ET: 22C4h
– Bottom Device Code M29W160EB: 2249h
Figure 1. Packages
TSOP48 (N)
12 x 20mm
FBGA
TFBGA48 (ZA)
6 x 8mm
January 2004
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M29W160ET pdf
M29W160ET, M29W160EB
SUMMARY DESCRIPTION
The M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Figures 5 and 6, Block Addresses.
The first or last 64 KBytes have been divided into
four additional blocks. The 16 KByte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 KByte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered TSOP48 (12 x 20mm) and
TFBGA48 (0.8mm pitch) packages. The memory
is supplied with all the bits erased (set to ’1’).
Figure 2. Logic Diagram
VCC
20
A0-A19
15
DQ0-DQ14
W
E
G
RP
BYTE
M29W160ET
M29W160EB
DQ15A–1
RB
VSS
AI06849B
Table 1. Signal Names
A0-A19
Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE
Byte/Word Organization Select
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
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M29W160ET arduino
M29W160ET, M29W160EB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 11, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
Write operation. See Figures 12 and 13, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations un-
til the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations. Additional bus opera-
tions can be performed to read the Electronic Sig-
nature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming equipment and are not usu-
ally used in applications. They require VID to be
applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2 and 3, Bus Operations.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Block Protect and Blocks Unprotect opera-
tions are described in Appendix C.
Table 2. Bus Operations, BYTE = VIL
Operation
E GW
Bus Read
VIL VIL VIH
Bus Write
VIL VIH VIL
Output Disable
X VIH VIH
Standby
VIH X
X
Read Manufacturer
Code
VIL
VIL
VIH
Read Device Code
VIL
VIL
VIH
Note: X = VIL or VIH.
Address Inputs
DQ15A–1, A0-A19
Data Inputs/Outputs
DQ14-DQ8
DQ7-DQ0
Cell Address
Hi-Z
Data Output
Command Address
Hi-Z
Data Input
X
Hi-Z
Hi-Z
X
Hi-Z
Hi-Z
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
Hi-Z
Hi-Z
20h
C4h (M29W160ET)
49h (M29W160EB)
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