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PDF M29W008T Data sheet ( Hoja de datos )
| Número de pieza | M29W008T | |
| Descripción | 8 Mbit 1Mb x8 / Boot Block Low Voltage Single Supply Flash Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M29W008T
M29W008B
8 Mbit (1Mb x8, Boot Block)
Low Voltage Single Supply Flash Memory
M29W008T and M29W008B are replaced
respectively by the M29W008AT and
M29W008AB
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 100ns
FAST PROGRAMMING TIME: 10µs typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M29W008T: D2h
– Device Code, M29W008B: DCh
DESCRIPTION
The M29W008 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single 2.7V to 3.6V VCC supply. For
Program and Erase operations the necessary high
voltages are generated internally. The device can
also be programmed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
NOT FOR NEW DESIGN
TSOP40 (N)
10 x 20 mm
Figure 1. Logic Diagram
VCC
20
A0-A19
8
DQ0-DQ7
W
M29W008T
E M29W008B RB
G
RP
VSS
AI02189
June 1999
This is information on a product still in production but not recommended for new designs.
1/30
1 page  
M29W008T, M29W008B
Figure 3B. Bottom Boot Block Memory Map and Block Address Table
BOTTOM BOOT BLOCK
Byte-Wide
FFFFFh
F0000h
EFFFFh
E0000h
DFFFFh
D0000h
CFFFFh
C0000h
BFFFFh
B0000h
AFFFFh
A0000h
9FFFFh
90000h
8FFFFh
80000h
7FFFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
00000h
Byte-Wide
32K MAIN BLOCK
8K PARAMETER BLOCK
8K PARAMETER BLOCK
16K BOOT BLOCK
0FFFFh
08000h
07FFFh
06000h
05FFFh
04000h
03FFFh
00000h
AI02136
5/30
5 Page 
M29W008T, M29W008B
Table 8. Instructions (1)
Mne.
Instr. Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
Addr. (3,7)
X
Read/Reset 1+
Read Memory Array until a new write cycle is initiated.
RD (2,4) Memory
Data
F0h
Array
Addr. (3,7) 5555h
3+
Data
AAh
2AAAh
55h
5555h Read Memory Array until a new write cycle
is initiated.
F0h
AS (4) Auto Select
Addr. (3,7) 5555h
3+
Data
AAh
2AAAh
55h
5555h Read Electronic Signature or Block
Protection Status until a new write cycle is
90h initiated. See Note 5 and 6.
PG Program
Addr. (3,7) 5555h
4
Data
AAh
2AAAh
55h
5555h
A0h
Program
Address
Program
Data
Read Data Polling or Toggle Bit
until Program completes.
6 Addr. (3,7) 5555h
BE Block Erase
2AAAh
5555h
5555h
2AAAh
Block Additional
Address Block (8)
Data
AAh 55h 80h AAh 55h 30h 30h
Chip Erase
CE
6 Addr. (3,7) 5555h
Data
AAh
2AAAh
55h
5555h
80h
5555h
AAh
2AAAh
55h
5555h
10h
Note 9
ES (10)
Erase
Suspend
Addr. (3,7)
1
X
Read until Toggle stops, then read all the data needed from any
Block(s) not being erased then Resume Erase.
Data
B0h
ER
Erase
Resume
Addr. (3,7)
1
X
Read Data Polling or Toggle Bits until Erase completes or Erase
is suspended another time
Data
30h
Notes: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation. (See Table 14 and Figure 9).
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
the command cycles.
5. Signature Address bits A0, A1 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1 at VIL will output
Device code.
6. Block Protection Address: A0 at VIL, A1 at VIH and A13-A19 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A15-A19 are don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status
can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered,
read Data Polling or Toggle bit until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
11/30
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